Tunable charge-trap memory based on few-layer MoS2

A carbonyl-decorated two-dimensional polymer as a charge-trapping layer for non-volatile memory storage devices with a high endurance and wide memory window

The charge-trapping mechanism in conjugated polymers is a performance obstacle in many optoelectronic devices harnessed for non-volatile memory applications. Herein, a carbonyl-decorated organic 2D-polymer (TpDb)-based charge-trapping memory device has been developed with a wide memory window (3.2 V) with low programming and erasing voltages of +3/-2 and -3/+2. The TpDb was synthesized by a potentially scalable solid-state aldol condensation reaction. The inherent structural defects and the semi-conjugated nature of the enone network in TpDb offer effective charge-trapping through the localization of charges in specific functional groups (CO). The interlayer hydrogen bonding enhances the packing density of the 2D-polymer layers thereby improving the memory storage properties of the material. Furthermore, the TpDb exhibits excellent features for non-volatile memory applications including over 10 000 cycles of write/read endurance and a prolonged retention performance of 104 seconds at high temperatures (100 °C).

2D Reconfigurable Memory Device Enabled by Defect Engineering for Multifunctional Neuromorphic Computing

In this era of artificial intelligence and Internet of Things, emerging new computing paradigms such as in-sensor and in-memory computing call for both structurally simple and multifunctional memory devices. Although emerging two-dimensional (2D) memory devices provide promising solutions, the most reported devices either suffer from single functionalities or structural complexity. Here, this work reports a reconfigurable memory device (RMD) based on MoS2/CuInP2S6 heterostructure, which integrates the defect engineering-enabled interlayer defects and the ferroelectric polarization in CuInP2S6, to realize a simplified structure device for all-in-one sensing, memory and computing. The plasma treatment-induced defect engineering of the CuInP2S6 nanosheet effectively increases the interlayer defect density, which significantly enhances the charge-trapping ability in synergy with ferroelectric properties. The reported device not only can serve as a non-volatile electronic memory device, but also can be reconfigured into optoelectronic memory mode or synaptic mode after controlling the ferroelectric polarization states in CuInP2S6. When operated in optoelectronic memory mode, the all-in-one RMD could diagnose ophthalmic disease by segmenting vasculature within biological retinas. On the other hand, operating as an optoelectronic synapse, this work showcases in-sensor reservoir computing for gesture recognition with high energy efficiency.

Ultrafast Non-Volatile Floating-Gate Memory Based on All-2D Materials

The explosive growth of massive-data storage and the demand for ultrafast data processing require innovative memory devices with exceptional performance. 2D materials and their van der Waal heterostructures with atomically sharp interfaces hold great promise for innovations in memory devices. Here, this work presents non-volatile, floating-gate memory devices with all functional layers made of 2D materials, achieving ultrafast programming/erasing speeds (20 ns), high extinction ratios (up to 108), and multi-bit storage capability. These devices also exhibit long-term data retention exceeding 10 years, facilitated by a high gate-coupling ratio (GCR) and atomically sharp interfaces between functional layers. Additionally, this work demonstrates the realization of an "OR" logic gate on a single-device unit by synergistic electrical and optical operations. The present results provide a solid foundation for next-generation ultrahigh-speed, ultralong lifespan, non-volatile memory devices, with a potential for scale-up manufacturing and flexible electronics applications.

Submicron Memtransistors Made from Monocrystalline Molybdenum Disulfide

Multiterminal memtransistors made from two-dimensional (2D) materials have garnered increasing attention in the pursuit of low-power heterosynaptic neuromorphic circuits. However, existing 2D memtransistors tend to necessitate high set voltages (>1 V) or feature defective channels, posing concerns regarding material integrity and intrinsic properties. Herein, we present a monocrystalline monolayer MoS2 memtransistor designed for operation within submicron regimes. Under reverse drain bias sweeps, our experiments reveal memristive behavior within the device, further controllable through modulation of the gate terminal. This controllability facilitates the consistent manifestation of multistate memory effects. Notably, the memtransistor behavior becomes more significant as the channel length diminishes, particularly with channel lengths below 1.6 μm, showcasing an increase in the switching ratio alongside a decrease in the set voltage with the decreasing channel length. Our optimized memtransistor demonstrates the ability to exhibit individual resistance states spanning 5 orders of magnitude, with switching drain voltages of approximately 0.05 V. To elucidate these findings, we investigate hot carrier effects and their interplay with oxide traps within the HfO2 dielectric. This work highlights the importance of memtransisor behavior in highly scaled 2D transistors, particularly those featuring low contact resistances. This understanding holds the potential to tailor memory characteristics essential for the development of energy-efficient neuromorphic devices.

Recent advances in 2D transition metal dichalcogenide-based photodetectors: a review

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as a highly promising platform for the development of photodetectors (PDs) owing to their remarkable electronic and optoelectronic properties. Highly effective PDs can be obtained by making use of the exceptional properties of 2D materials, such as their high transparency, large charge carrier mobility, and tunable electronic structure. The photodetection mechanism in 2D TMD-based PDs is thoroughly discussed in this article, with special attention paid to the key characteristics that set them apart from PDs based on other integrated materials. This review examines how single TMDs, TMD-TMD heterostructures, TMD-graphene (Gr) hybrids, TMD-MXene composites, TMD-perovskite heterostructures, and TMD-quantum dot (QD) configurations show advanced photodetection. Additionally, a thorough analysis of the recent developments in 2D TMD-based PDs, highlighting their exceptional performance capabilities, including ultrafast photo response, ultrabroad detectivity, and ultrahigh photoresponsivity, attained through cutting-edge methods is provided. The article conclusion highlights the potential for ground-breaking discoveries in this fast developing field of research by outlining the challenges faced in the field of PDs today and providing an outlook on the prospects of 2D TMD-based PDs in the future.

A 2D Heterostructure-Based Multifunctional Floating Gate Memory Device for Multimodal Reservoir Computing

The demand for economical and efficient data processing has led to a surge of interest in neuromorphic computing based on emerging two-dimensional (2D) materials in recent years. As a rising van der Waals (vdW) p-type Weyl semiconductor with many intriguing properties, tellurium (Te) has been widely used in advanced electronics/optoelectronics. However, its application in floating gate (FG) memory devices for information processing has never been explored. Herein, an electronic/optoelectronic FG memory device enabled by Te-based 2D vdW heterostructure for multimodal reservoir computing (RC) is reported. When subjected to intense electrical/optical stimuli, the device exhibits impressive nonvolatile electronic memory behaviors including ≈108 extinction ratio, ≈100 ns switching speed, >4000 cycles, >4000-s retention stability, and nonvolatile multibit optoelectronic programmable characteristics. When the input stimuli weaken, the nonvolatile memory degrades into volatile memory. Leveraging these rich nonlinear dynamics, a multimodal RC system with high recognition accuracy of 90.77% for event-type multimodal handwritten digit-recognition is demonstrated.

Three-dimensional integration of two-dimensional field-effect transistors

In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as 'More Moore'1 but also introduces multifunctionalities for 'More than Moore'2 technologies. Although silicon-based 3D integrated circuits are commercially available3-5, there is limited effort on 3D integration of emerging nanomaterials6,7 such as two-dimensional (2D) materials despite their unique functionalities7-10. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length, LCH = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension.

Highly Reliable Van Der Waals Memory Boosted by a Single 2D Charge Trap Medium

Charge trap materials that can store carriers efficiently and controllably are desired for memory applications. 2D materials are promising for highly compacted and reliable memory mainly due to their ease of constructing atomically uniform interfaces, however, remain unexplored as being charge trap media. Here it is discovered that 2D semiconducting PbI2 is an excellent charge trap material for nonvolatile memory and artificial synapses. It is simple to construct PbI2 -based charge trap devices since no complicated synthesis or additional defect manufacturing are required. As a demonstration, MoS2 /PbI2 device exhibits a large memory window of 120 V, fast write speed of 5 µs, high on-off ratio around 106 , multilevel memory of over 8 distinct states, high reliability with endurance up to 104 cycles and retention over 1.2 × 104 s. It is envisioned that PbI2 with ionic activity caused by the natively formed iodine vacancies is unique to combine with unlimited 2D materials for versatile van der Waals devices with high-integration and multifunctionality.

Study of Ion Velocity Effect on the Band Gap of CVD-Grown Few-Layer MoS2

The present work reports on a simple chemical vapor deposition (CVD) technique that employs alkali halide (NaCl) to synthesize high-quality few-layer MoS2 by reducing growth temperature from 850 to 650 °C, and its ion irradiation study for band gap modification. The Raman peak position difference of A1g to E12g of ≈24.5 cm-1 for the synthesized MoS2 corresponds to a few layers (<5 monolayers) of MoS2 on the substrate, as also confirmed by atomic force microscopy (AFM). The optical image shows the continuous distribution of flakes throughout the substrate and the average area of flakes ≈0.2 μm2 as confirmed by scanning electron microscopy (SEM) and transmission electron microscopy (TEM) analysis. Swift heavy-ion (SHI) irradiation at 60, 100, and 150 MeV ion energies of 1 × 1012 ions/cm2 ion fluence have been used to modify the band gap in few-layer MoS2. The ions with two different energies are chosen at two sides of the Bragg peak of energy loss curve in such a way as to have the same value of electronic energy loss (Se) but different ion energies to examine the velocity effect for the ion-induced modification. The absorbance peaks for 60 and 150 MeV irradiated samples show the same effect in the band gap modification.

Manipulation of the electrical and memory properties of MoS2 field-effect transistors by highly charged ion irradiation

Field-effect transistors based on molybdenum disulfide (MoS2) exhibit a hysteresis in their transfer characteristics, which can be utilized to realize 2D memory devices. This hysteresis has been attributed to charge trapping due to adsorbates, or defects either in the MoS2 lattice or in the underlying substrate. We fabricated MoS2 field-effect transistors on SiO2/Si substrates, irradiated these devices with Xe30+ ions at a kinetic energy of 180 keV to deliberately introduce defects and studied the resulting changes of their electrical and hysteretic properties. We find clear influences of the irradiation: while the charge carrier mobility decreases linearly with increasing ion fluence (up to only 20% of its initial value) the conductivity actually increases again after an initial drop of around two orders of magnitude. We also find a significantly reduced n-doping (≈1012 cm-2) and a well-developed hysteresis after the irradiation. The hysteresis height increases with increasing ion fluence and enables us to characterize the irradiated MoS2 field-effect transistor as a memory device with remarkably longer relaxation times (≈ minutes) compared to previous works.

High-Speed Optoelectronic Nonvolatile Memory Based on van der Waals Heterostructures

High-performance optoelectronic nonvolatile memory is promising candidate for next-generation information memory devices. Here, a floating-gate memory is constructed based on van der Waals heterostructure, which exhibits a large storage window ratio (≈75.5%) and an extremely high on/off ratio (107 ), as well as an ultrafast electrical writing/erasing speed (40 ns). The enhanced performance enables as-fabricated devices to present excellent multilevel data storage, robust retention, and endurance performance. Moreover, stable optical erasing operations can be achieved by illuminating the device with a laser pulse, showcasing outstanding optoelectronic storage performance (optical erasing speed ≈ 2.3 ms). The nonvolatile and high-speed characteristics of these devices hold significant potential for the integration of high-performance nonvolatile memory.

Probing Optical Multi-Level Memory Effects in Single Core-Shell Quantum Dots and Application Through 2D-0D Hybrid Inverters

Challenges in the development of a multi-level memory (MM) device for multinary arithmetic computers have posed an obstacle to low-power, ultra-high-speed operation. For the effective transfer of a huge amount of data between arithmetic and storage devices, optical communication technology represents a compelling solution. Here, by replicating a floating gate architecture with CdSe/ZnS type-I core/shell quantum dots (QDs), a 2D-0D hybrid optical multi-level memory (OMM) device operated is demonstrated by laser pulses. In the device, laser pulses create linear optically trapped currents with MM characteristics, while conversely, voltage pulses reset all the trapped currents at once. Assuming electron transfer via the energy band alignment between MoS2 and CdSe, the study also establishes the mechanism of the OMM effect. Analysis of the designed device led to a new hypothesis that charge transfer is difficult for laterally adjacent QDs facing a double ZnS shell, which is tested by separately stimulating different positions on the 2D-0D hybrid structure with finely focused laser pulses. Results indicate that each laser pulse induced independent MM characteristics in the 2D-0D hybrid architecture. Based on this phenomenon, we propose a MM inverter to produce MM effects, such as programming and erasing, solely through the use of laser pulses. Finally, the feasibility of a fully optically-controlled intelligent system based on the proposed OMM inverters is evaluated through a CIFAR-10 pattern recognition task using a convolutional neural network.

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells-e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.

Uncovering the Role of Crystal Phase in Determining Nonvolatile Flash Memory Device Performance Fabricated from MoTe2-Based 2D van der Waals Heterostructures

Although the crystal phase of two-dimensional (2D) transition metal dichalcogenides (TMDs) has been proven to play an essential role in fabricating high-performance electronic devices in the past decade, its effect on the performance of 2D material-based flash memory devices still remains unclear. Here, we report the exploration of the effect of MoTe₂ in different phases as the charge-trapping layer on the performance of 2D van der Waals (vdW) heterostructure-based flash memory devices, where a metallic 1T'-MoTe₂ or semiconducting 2H-MoTe₂ nanoflake is used as the floating gate. By conducting comprehensive measurements on the two kinds of vdW heterostructure-based devices, the memory device based on MoS₂/h-BN/1T'-MoTe₂ presents much better performance, including a larger memory window, faster switching speed (100 ns), and higher extinction ratio (10⁷), than that of the device based on the MoS₂/h-BN/2H-MoTe₂ heterostructure. Moreover, the device based on the MoS₂/h-BN/1T'-MoTe₂ heterostructure also shows a long cycle (>1200 cycles) and retention (>3000 s) stability. Our study clearly demonstrates that the crystal phase of 2D TMDs has a significant impact on the performance of nonvolatile flash memory devices based on 2D vdW heterostructures, which paves the way for the fabrication of future high-performance memory devices based on 2D materials.

Thermally Driven Multilevel Non-Volatile Memory with Monolayer MoS2 for Brain-Inspired Artificial Learning

The demands of modern electronic components require advanced computing platforms for efficient information processing to realize in-memory operations with a high density of data storage capabilities toward developing alternatives to von Neumann architectures. Herein, we demonstrate the multifunctionality of monolayer MoS₂ memtransistors, which can be used as a high-geared intrinsic transistor at room temperature; however, at a high temperature (>350 K), they exhibit synaptic multilevel memory operations. The temperature-dependent memory mechanism is governed by interfacial physics, which solely depends on the gate field modulated ion dynamics and charge transfer at the MoS₂/dielectric interface. We have proposed a non-volatile memory application using a single Field Effect Transistor (FET) device where thermal energy can be ventured to aid the memory functions with multilevel (3-bit) storage capabilities. Furthermore, our devices exhibit linear and symmetry in conductance weight updates when subjected to electrical potentiation and depression. This feature has enabled us to attain a high classification accuracy while training and testing the Modified National Institute of Standards and Technology datasets through artificial neural network simulation. This work paves the way toward reliable data processing and storage using 2D semiconductors with high-packing density arrays for brain-inspired artificial learning.

Photoluminescence of Two-Dimensional MoS2 Nanosheets Produced by Liquid Exfoliation

Extraordinary properties of two-dimensional materials make them attractive for applications in different fields. One of the prospective niches is optical applications, where such types of materials demonstrate extremely sensitive performance and can be used for labeling. However, the optical properties of liquid-exfoliated 2D materials need to be analyzed. The purpose of this work is to study the absorption and luminescent properties of MoS₂ exfoliated in the presence of sodium cholate, which is the most often used surfactant. Ultrasound bath and mixer-assisted exfoliation in water and dimethyl sulfoxide were used. The best quality of MoS₂ nanosheets was achieved using shear-assisted liquid-phase exfoliation as a production method and sodium cholate (SC) as a surfactant. The photoluminescent properties of MoS₂ nanosheets varied slightly when changing the surfactant concentrations in the range C(SC) = 0.5-2.5 mg/mL. This work is of high practical importance for further enhancement of MoS₂ photoluminescent properties via chemical functionalization.

2D materials readiness for the transistor performance breakthrough

As the size of the transistor scales down, this strategy has confronted challenges because of the fundamental limits of silicon materials. Besides, more and more energy and time are consumed by the data transmission out of transistor computing because of the speed mismatching between the computing and memory. To meet the energy efficiency demands of big data computing, the transistor should have a smaller feature size and store data faster to overcome the energy burden of computing and data transfer. Electron transport in two-dimensional (2D) materials is constrained within a 2D plane and different materials are assembled by the van der Waals force. Owning to the atomic thickness and dangling-bond-free surface, 2D materials have demonstrated advantages in transistor scaling-down and heterogeneous structure innovation. In this review, from the performance breakthrough of 2D transistors, we discuss the opportunities, progress and challenges of 2D materials in transistor applications.

Artificial visual perception neural system using a solution-processable MoS2-based in-memory light sensor

Optoelectronic devices are advantageous in in-memory light sensing for visual information processing, recognition, and storage in an energy-efficient manner. Recently, in-memory light sensors have been proposed to improve the energy, area, and time efficiencies of neuromorphic computing systems. This study is primarily focused on the development of a single sensing-storage-processing node based on a two-terminal solution-processable MoS₂ metal-oxide-semiconductor (MOS) charge-trapping memory structure-the basic structure for charge-coupled devices (CCD)-and showing its suitability for in-memory light sensing and artificial visual perception. The memory window of the device increased from 2.8 V to more than 6 V when the device was irradiated with optical lights of different wavelengths during the program operation. Furthermore, the charge retention capability of the device at a high temperature (100 °C) was enhanced from 36 to 64% when exposed to a light wavelength of 400 nm. The larger shift in the threshold voltage with an increasing operating voltage confirmed that more charges were trapped at the Al₂O₃/MoS₂ interface and in the MoS₂ layer. A small convolutional neural network was proposed to measure the optical sensing and electrical programming abilities of the device. The array simulation received optical images transmitted using a blue light wavelength and performed inference computation to process and recognize the images with 91% accuracy. This study is a significant step toward the development of optoelectronic MOS memory devices for neuromorphic visual perception, adaptive parallel processing networks for in-memory light sensing, and smart CCD cameras with artificial visual perception capabilities.

Gate Dielectrics Integration for 2D Electronics: Challenges, Advances, and Outlook

2D semiconductors have emerged both as an ideal platform for fundamental studies and as promising channel materials in beyond-silicon field-effect-transistors due to their outstanding electrical properties and exceptional tunability via external field. However, the lack of proper dielectrics for 2D semiconductors has become a major roadblock for their further development toward practical applications. The prominent issues between conventional 3D dielectrics and 2D semiconductors arise from the integration and interface quality, where defect states and imperfections lead to dramatic deterioration of device performance. In this review article, the root causes of such issues are briefly analyzed and recent advances on some possible solutions, including various approaches of adapting conventional dielectrics to 2D semiconductors, and the development of novel dielectrics with van der Waals surface toward high-performance 2D electronics are summarized. Then, in the perspective, the requirements of ideal dielectrics for state-of-the-art 2D devices are outlined and an outlook for their future development is provided.

High-Performance C60 Coupled Ferroelectric Enhanced MoS2 Nonvolatile Memory

Nonvolatile memory (NVM) devices based on two-dimensional (2D) materials have recently attracted widespread attention due to their high-density integration potential and the ability to be applied in computing-in-memory systems in the post-Moore era. Considering the high current on/off ratio, programmable threshold voltage, nonvolatile multilevel memory state, and extended logic functions, plenty of breakthroughs related to ferroelectric field-effect transistors (FeFETs), one of the most important NVM devices, have been made in the past decade. Among them, FETs coupled with organic ferroelectric films such as P(VDF-TrFE) displayed properties of remarkable robustness, easy preparation, and low cost. However, the dipoles of the P(VDF-TrFE) film cannot be flipped smoothly at low voltage, impeding the further application of organic FeFET. In this paper, we proposed a high-performance FeFET based on monolayer MoS₂ coupled with C₆₀ doped ferroelectric copolymer P(VDF-TrFE). The inserted C₆₀ molecules enhanced the alignment of the dipoles effectively at low voltage, allowing the modified device to demonstrate a large memory window (∼16 V), high current on/off ratio (>10⁶), long retention time (>10 000 s), and remarkable endurance under the reduced operating voltage. In addition, the in situ logic application can be realized by constructing facile device interconnection without building complex complementary semiconductor circuits. Our results are expected to pave the way for future low-consumption computing-in-memory applications based on high-quality 2D FeFETs.

Combination of Polymer Gate Dielectric and Two-Dimensional Semiconductor for Emerging Field-Effect Transistors

Two-dimensional (2D) materials are considered attractive semiconducting layers for emerging field-effect transistors owing to their unique electronic and optoelectronic properties. Polymers have been utilized in combination with 2D semiconductors as gate dielectric layers in field-effect transistors (FETs). Despite their distinctive advantages, the applicability of polymer gate dielectric materials for 2D semiconductor FETs has rarely been discussed in a comprehensive manner. Therefore, this paper reviews recent progress relating to 2D semiconductor FETs based on a wide range of polymeric gate dielectric materials, including (1) solution-based polymer dielectrics, (2) vacuum-deposited polymer dielectrics, (3) ferroelectric polymers, and (4) ion gels. Exploiting appropriate materials and corresponding processes, polymer gate dielectrics have enhanced the performance of 2D semiconductor FETs and enabled the development of versatile device structures in energy-efficient ways. Furthermore, FET-based functional electronic devices, such as flash memory devices, photodetectors, ferroelectric memory devices, and flexible electronics, are highlighted in this review. This paper also outlines challenges and opportunities in order to help develop high-performance FETs based on 2D semiconductors and polymer gate dielectrics and realize their practical applications.

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. The different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

The Road for 2D Semiconductors in the Silicon Age

Continued reduction in transistor size can improve the performance of silicon integrated circuits (ICs). However, as Moore's law approaches physical limits, high-performance growth in silicon ICs becomes unsustainable, due to challenges of scaling, energy efficiency, and memory limitations. The ultrathin layers, diverse band structures, unique electronic properties, and silicon-compatible processes of 2D materials create the potential to consistently drive advanced performance in ICs. Here, the potential of fusing 2D materials with silicon ICs to minimize the challenges in silicon ICs, and to create technologies beyond the von Neumann architecture, is presented, and the killer applications for 2D materials in logic and memory devices to ease scaling, energy efficiency bottlenecks, and memory dilemmas encountered in silicon ICs are discussed. The fusion of 2D materials allows the creation of all-in-one perception, memory, and computation technologies beyond the von Neumann architecture to enhance system efficiency and remove computing power bottlenecks. Progress on the 2D ICs demonstration is summarized, as well as the technical hurdles it faces in terms of wafer-scale heterostructure growth, transfer, and compatible integration with silicon ICs. Finally, the promising pathways and obstacles to the technological advances in ICs due to the integration of 2D materials with silicon are presented.

Low-voltage ultrafast nonvolatile memory via direct charge injection through a threshold resistive-switching layer

The explosion in demand for massive data processing and storage requires revolutionary memory technologies featuring ultrahigh speed, ultralong retention, ultrahigh capacity and ultralow energy consumption. Although a breakthrough in ultrafast floating-gate memory has been achieved very recently, it still suffers a high operation voltage (tens of volts) due to the Fowler-Nordheim tunnelling mechanism. It is still a great challenge to realize ultrafast nonvolatile storage with low operation voltage. Here we propose a floating-gate memory with a structure of MoS₂/hBN/MoS₂/graphdiyne oxide/WSe₂, in which a threshold switching layer, graphdiyne oxide, instead of a dielectric blocking layer in conventional floating-gate memories, is used to connect the floating gate and control gate. The volatile threshold switching characteristic of graphdiyne oxide allows the direct charge injection from control gate to floating gate by applying a nanosecond voltage pulse (20 ns) with low magnitude (2 V), and restricts the injected charges in floating gate for a long-term retention (10 years) after the pulse. The high operation speed and low voltage endow the device with an ultralow energy consumption of 10 fJ. These results demonstrate a new strategy to develop next-generation high-speed low-energy nonvolatile memory.

2D materials: increscent quantum flatland with immense potential for applications

Quantum flatland i.e., the family of two dimensional (2D) quantum materials has become increscent and has already encompassed elemental atomic sheets (Xenes), 2D transition metal dichalcogenides (TMDCs), 2D metal nitrides/carbides/carbonitrides (MXenes), 2D metal oxides, 2D metal phosphides, 2D metal halides, 2D mixed oxides, etc. and still new members are being explored. Owing to the occurrence of various structural phases of each 2D material and each exhibiting a unique electronic structure; bestows distinct physical and chemical properties. In the early years, world record electronic mobility and fractional quantum Hall effect of graphene attracted attention. Thanks to excellent electronic mobility, and extreme sensitivity of their electronic structures towards the adjacent environment, 2D materials have been employed as various ultrafast precision sensors such as gas/fire/light/strain sensors and in trace-level molecular detectors and disease diagnosis. 2D materials, their doped versions, and their hetero layers and hybrids have been successfully employed in electronic/photonic/optoelectronic/spintronic and straintronic chips. In recent times, quantum behavior such as the existence of a superconducting phase in moiré hetero layers, the feasibility of hyperbolic photonic metamaterials, mechanical metamaterials with negative Poisson ratio, and potential usage in second/third harmonic generation and electromagnetic shields, etc. have raised the expectations further. High surface area, excellent young's moduli, and anchoring/coupling capability bolster hopes for their usage as nanofillers in polymers, glass, and soft metals. Even though lab-scale demonstrations have been showcased, large-scale applications such as solar cells, LEDs, flat panel displays, hybrid energy storage, catalysis (including water splitting and CO₂ reduction), etc. will catch up. While new members of the flatland family will be invented, new methods of large-scale synthesis of defect-free crystals will be explored and novel applications will emerge, it is expected. Achieving a high level of in-plane doping in 2D materials without adding defects is a challenge to work on. Development of understanding of inter-layer coupling and its effects on electron injection/excited state electron transfer at the 2D-2D interfaces will lead to future generation heterolayer devices and sensors.

Photoinduced Multi-Bit Nonvolatile Memory Based on a van der Waals Heterostructure with a 2D-Perovskite Floating Gate

The development of floating-gate nonvolatile memory (FGNVM) is limited by the charge storage, retention and transfer ability of the charge-trapping layer. Here, it is demonstrated that due to the unique alternate inorganic/organic chain structure and superior optical sensitivity, an insulating 2D Ruddlesden-Popper perovskite (2D-RPP) layer can function both as an excellent charge-storage layer and a photosensitive layer. Optoelectronic memory composed of a MoS₂ /hBN/2D-RPP (MBR) van der Waals heterostructure is demonstrated. The MBR device exhibits unique light-controlled charge-storage characteristics, with maximum memory window up to 92 V, high on/off ratio of 10⁴ , negligible degeneration over 10³  s, >1000 program/erase cycles, and write speed of 500 µs. Dependent on the initial states, the MBR optoelectronic memory can be programmed in both positive photoconductivity (PPC) and negative photoconductivity (NPC) modes, with up to 11 and 22 distinct resistance states, respectively. The optical program power for each bit is as low as 36/10 pJ for PPC/NPC. The results not only reveal the potential of 2D-RPP as a superior charge-storage medium in floating-gate memory, but also provides an effective strategy toward fast, low-power and stable optical multi-bit storage and neuromorphic computing.

Reconfigurable Quasi-Nonvolatile Memory/Subthermionic FET Functions in Ferroelectric-2D Semiconductor vdW Architectures

The functional reconfiguration of transistors and memory in homogenous ferroelectric devices offers significant opportunities for implementing the concepts of in-memory computing and logic-memory monolithic integration. Thus far, reconfiguration is realized through programmable doping profiles in the semiconductor channel using multiple-gate operation. This complex device architecture limits further scaling to match the overall chip requirements. Here, reconfigurable memory/transistor functionalities in a ferroelectric-gated van der Waals transistor by controlling the behavior of ferroelectric oxygen vacancies at the interface are demonstrated. Short- and long-term memory functions are demonstrated by modulating the border oxygen vacancy distribution and the associated charge dynamics. The quasi-nonvolatile long-term memory exhibits data retention of over 10⁵ s and endurance of up to 5 × 10⁵ cycles, verifying its applicability as a potential device platform for neuromorphic networks. More importantly, by modulating the ferroelectricity of the interfacial domains with the interactions of oxygen vacancies, a hysteresis-free logic transistor is realized with a subthermionic subthreshold swing down to 46 mV dec^-1 , which resembles a negative-capacitance field-effect transistor. The new concept of achieving functional reconfiguration with prior device performance in a single-gate ferroelectric field-effect transistor is of great advantage in future integrated circuit applications.

Programmable black phosphorus image sensor for broadband optoelectronic edge computing

Image sensors with internal computing capability enable in-sensor computing that can significantly reduce the communication latency and power consumption for machine vision in distributed systems and robotics. Two-dimensional semiconductors have many advantages in realizing such intelligent vision sensors because of their tunable electrical and optical properties and amenability for heterogeneous integration. Here, we report a multifunctional infrared image sensor based on an array of black phosphorous programmable phototransistors (bP-PPT). By controlling the stored charges in the gate dielectric layers electrically and optically, the bP-PPT’s electrical conductance and photoresponsivity can be locally or remotely programmed with 5-bit precision to implement an in-sensor convolutional neural network (CNN). The sensor array can receive optical images transmitted over a broad spectral range in the infrared and perform inference computation to process and recognize the images with 92% accuracy. The demonstrated bP image sensor array can be scaled up to build a more complex vision-sensory neural network, which will find many promising applications for distributed and remote multispectral sensing.

2D materials represent a promising platform for machine vision and edge computing applications, although usually limited to ultraviolet and visible wavelengths. Here, the authors report the realization of a programmable image sensor based on black phosphorus, implementing multispectral imaging and analog in-memory computing functionalities in the near- to mid-infrared range.

Memristive Devices Based on Two-Dimensional Transition Metal Chalcogenides for Neuromorphic Computing

Two-dimensional (2D) transition metal chalcogenides (TMC) and their heterostructures are appealing as building blocks in a wide range of electronic and optoelectronic devices, particularly futuristic memristive and synaptic devices for brain-inspired neuromorphic computing systems. The distinct properties such as high durability, electrical and optical tunability, clean surface, flexibility, and LEGO-staking capability enable simple fabrication with high integration density, energy-efficient operation, and high scalability. This review provides a thorough examination of high-performance memristors based on 2D TMCs for neuromorphic computing applications, including the promise of 2D TMC materials and heterostructures, as well as the state-of-the-art demonstration of memristive devices. The challenges and future prospects for the development of these emerging materials and devices are also discussed. The purpose of this review is to provide an outlook on the fabrication and characterization of neuromorphic memristors based on 2D TMCs.

WSe2/WS2 Heterobilayer Nonvolatile Memory Device with Boosted Charge Retention

A two-dimensional (2D) nonvolatile memory device architecture to improve the long-term charge retention with the minimum charge loss without compromising storage capacity and the extinction ratio for practical applications has been an imminent demand. To address the current issue, we adopted a novel type-II band-aligned heterobilayer channel comprising vertically stacked monolayer WSe₂ nanodots on monolayer WS₂. The band offset modulation leads to electron doping from WSe₂ nanodots into the WS₂ channel without any external driving electric field. As a result, the tested device outperformed with a memory window as high as 34 V and a negligible charge loss of 7% in a retention period of 10 years while maintaining a high extinction ratio of 10⁶. The doping technique presented in this work provides a feasible route to modulate the electrical properties of 2D channel materials without hampering charge transport, paving the way for high-performance 2D memory devices.

Resistance Switching Effect of Memory Device Based on All-Inorganic Cspbbri2 Perovskite

In this study, the CsPbBrI₂ perovskite film was prepared by the preparation of the sol-gel and the spin-coating method, and the cubic lattice was stabilized by introducing Br⁺ into the CsPbI₃ film, which solved the problem of instability of the traditional perovskite phase. Based on the CsPbBrI₂ perovskite film, the Ag/CsPbBrI₂/ITO memory device with a resistance switching effect was prepared. The morphology and phase compositions of the film were analyzed by scanning electron microscope and X-ray diffraction. The non-volatile and repeatable resistance switching effect of the Ag/CsPbBrI₂/ITO memory device was measured under open-air conditions. The experimental results show that the surface of the CsPbBrI₂ perovskite film is uniform and dense, and the Ag/CsPbBrI₂/ITO memory device has an order of magnitude resistance-on-off ratio after 500 cycles of cyclic voltage. This study shows that Ag/CsPbBrI₂/ITO memory devices based on CsPbBrI₂ perovskite films have potential applications in the field of non-volatile memory devices. At the same time, the transient properties of the CsPbBrI₂ film that can quickly dissolve in deionized water make it potentially useful in short-period data storage units and implantable electronic devices with human or environmental sensors.

Atomically sharp interface enabled ultrahigh-speed non-volatile memory devices

The development of high-performance memory devices has played a key role in the innovation of modern electronics. Non-volatile memory devices have manifested high capacity and mechanical reliability as a mainstream technology; however, their performance has been hampered by low extinction ratio and slow operational speed. Despite substantial efforts to improve these characteristics, typical write times of hundreds of micro- or milliseconds remain a few orders of magnitude longer than that of their volatile counterparts. Here we demonstrate non-volatile, floating-gate memory devices based on van der Waals heterostructures with atomically sharp interfaces between different functional elements, achieving ultrahigh-speed programming/erasing operations in the range of nanoseconds with extinction ratio up to 10¹⁰. This enhanced performance enables new device capabilities such as multi-bit storage, thus opening up applications in the realm of modern nanoelectronics and offering future fabrication guidelines for device scale up.

Ultrafast non-volatile flash memory based on van der Waals heterostructures

Flash memory has become a ubiquitous solid-state memory device widely used in portable digital devices, computers and enterprise applications. The development of the information age has demanded improvements in memory speed and retention performance. Here we demonstrate an ultrafast non-volatile flash memory based on MoS₂/hBN/multilayer graphene van der Waals heterostructures, which achieves an ultrafast writing/erasing speed of 20 ns through two-triangle-barrier modified Fowler-Nordheim tunnelling. Using detailed theoretical analysis and experimental verification, we postulate that a suitable barrier height, gate coupling ratio and clean interface are the main reasons for the breakthrough writing/erasing speed of our flash memory devices. Because of its non-volatility this ultrafast flash memory could provide the foundation for the next generation of high-speed non-volatile memory.

Emerging 2D Memory Devices for In-Memory Computing

It is predicted that the conventional von Neumann computing architecture cannot meet the demands of future data-intensive computing applications due to the bottleneck between the processing and memory units. To try to solve this problem, in-memory computing technology, where calculations are carried out in situ within each nonvolatile memory unit, has been intensively studied. Among various candidate materials, 2D layered materials have recently demonstrated many new features that have been uniquely exploited to build next-generation electronics. Here, the recent progress of 2D memory devices is reviewed for in-memory computing. For each memory configuration, their operation mechanisms and memory characteristics are described, and their pros and cons are weighed. Subsequently, their versatile applications for in-memory computing technology, including logic operations, electronic synapses, and random number generation are presented. Finally, the current challenges and potential strategies for future 2D in-memory computing systems are also discussed at the material, device, circuit, and architecture levels. It is hoped that this manuscript could give a comprehensive review of 2D memory devices and their applications in in-memory computing, and be helpful for this exciting research area.

Investigation of charge trapping mechanism in MoS2field effect transistor by incorporating Al into host La2O3as gate dielectric

The charge trapping effect plays a key role in multi-bit memory devices and brain-like neuron devices. Herein, MoS₂field effect transistors are fabricated, incorporating Al into host La₂O₃as the gate dielectric, which exhibit excellent electrical properties with an on-off ratio in the memory window of ∼10⁶and a memory window ratio of ∼40%. Furthermore, the charge trapping and de-trapping processes were systematically studied, and the time constants are obtained from time-domain characteristics. Making use of the charge trapping effect, the threshold voltage of the device can be continuously adjusted. The oxide layer trap density and the interface state trap density are extracted using the charge separation method. These theoretical studies provide a deeper understanding of ways to control the charge trapping process, benefitting the commercialization of two-dimensional electronic devices and the development of new charge trapping devices.

Material and Device Structure Designs for 2D Memory Devices Based on the Floating Gate Voltage Trajectory

Two-dimensional heterostructures have been extensively investigated as next-generation nonvolatile memory (NVM) devices. In the past decade, drastic performance improvements and further advanced functionalities have been demonstrated. However, this progress is not sufficiently supported by the understanding of their operations, obscuring the material and device structure design policy. Here, detailed operation mechanisms are elucidated by exploiting the floating gate (FG) voltage measurements. Systematic comparisons of MoTe₂, WSe₂, and MoS₂ channel devices revealed that the tunneling behavior between the channel and FG is controlled by three kinds of current-limiting paths, i.e., tunneling barrier, 2D/metal contact, and p-n junction in the channel. Furthermore, the control experiment indicated that the access region in the device structure is required to achieve 2D channel/FG tunneling by preventing electrode/FG tunneling. The present understanding suggests that the ambipolar 2D-based FG-type NVM device with the access region is suitable for further realizing potentially high electrical reliability.

High-Performance Non-Volatile InGaZnO Based Flash Memory Device Embedded with a Monolayer Au Nanoparticles

Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔVth) of 13.7 V when it sweeps from -20 V to +20 V back and forth. Additionally, the material characteristics of the monolayer AuNPs (floating gate layer) and IGZO film (semiconductor layer) are confirmed using transmission electronic microscopy (TEM), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) techniques. The memory operations in terms of endurance and retention are obtained, revealing highly stable endurance properties of the device up to 100 P/E cycles by applying pulses (±20 V, duration of 100 ms) and reliable retention time up to 104 s. The proposed NVM device, owing to the properties of large memory window, stable endurance, and high retention time, enables an excellent approach in futuristic non-volatile memory technology.

Design and tailoring of two-dimensional Schottky, PN and tunnelling junctions for electronics and optoelectronics

Owing to their superior carrier mobility, strong light-matter interactions, and flexibility at the atomically thin thickness, two-dimensional (2D) materials are attracting wide interest for application in electronic and optoelectronic devices, including rectifying diodes, transistors, memory, photodetectors, and light-emitting diodes. At the heart of these devices, Schottky, PN, and tunneling junctions are playing an essential role in defining device function. Intriguingly, the ultrathin thickness and unique van der Waals (vdW) interlayer coupling in 2D materials has rendered enormous opportunities for the design and tailoring of various 2D junctions, e.g. using Lego-like hetero-stacking, surface decoration, and field-effect modulation methods. Such flexibility has led to marvelous breakthroughs during the exploration of 2D electronics and optoelectronic devices. To advance further, it is imperative to provide an overview of existing strategies for the engineering of various 2D junctions for their integration in the future. Thus, in this review, we provide a comprehensive survey of previous efforts toward 2D Schottky, PN, and tunneling junctions, and the functional devices built from them. Though these junctions exhibit similar configurations, distinct strategies have been developed for their optimal figures of merit based on their working principles and functional purposes.

Embedment of Multiple Transition Metal Impurities into WS2 Monolayer for Bandstructure Modulation

Band structure by design in 2D layered semiconductors is highly desirable, with the goal to acquire the electronic properties of interest through the engineering of chemical composition, structure, defect, stacking, or doping. For atomically thin transition metal dichalcogenides, substitutional doping with more than one single type of transition metals is the task for which no feasible approach is proposed. Here, the growth of WS₂ monolayer is shown codoped with multiple kinds of transition metal impurities via chemical vapor deposition controlled in a diffusion-limited mode. Multielement embedment of Cr, Fe, Nb, and Mo into the host lattice is exemplified. Abundant impurity states thus generate in the bandgap of the resultant WS₂ and provide a robust switch of charging/discharging states upon sweep of an electric filed. A profound memory window exists in the transfer curves of doped WS₂ field-effect transistors, forming the basis of binary states for robust nonvolatile memory. The doping technique presented in this work brings one step closer to the rational design of 2D semiconductors with desired electronic properties.

Multistate Memory Enabled by Interface Engineering Based on Multilayer Tungsten Diselenide

The diversification of data types and the explosive increase of data size in the information era continuously required to miniaturize the memory devices with high data storage capability. Atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) are promising candidates for flexible and transparent electronic and optoelectronic devices with high integration density. Multistate memory devices based on TMDs could possess high data storage capability with a large integration density and thus exhibit great potential applications in the field of data storage. Here, we report the multistate data storage based on multilayer tungsten diselenide (WSe₂) transistors by interface engineering. The multiple resistance states of the WSe₂ transistors are achieved by applying different gate voltage pulses, and the switching ratio of the memory can be as large as 10⁵ with high cycling endurance. The water and oxygen molecules (H₂O/O₂) trapped at the interface between the SiO₂ substrate and WSe₂ introduce the trap states and thus the large hysteresis of the transfer curves, which leads to the multistate data storage. In addition, the laminated Au thin film electrodes make the contact interface between the electrodes and WSe₂ free of dangling bond and Fermi level pinning, thus giving rise to the excellent performance of memory devices. Importantly, the interface trap states can be easily controlled by a simple oxygen plasma treatment of the SiO₂ substrate, and subsequently, the performance of the multistate memory devices can be manipulated. Our findings provide a simple and efficient strategy to engineer the interface states for the multistate data storage applications and would motivate more investigations on the trap state-associated applications.

A 2D material-based floating gate device with linear synaptic weight update

Neuromorphic computing is of great interest among researchers interested in overcoming the von Neumann computing bottleneck. A synaptic device, one of the key components to realize a neuromorphic system, has a weight that indicates the strength of the connection between two neurons, and updating this weight must have linear and symmetric characteristics. Especially, a transistor-type device has a gate terminal, separating the processes of reading and updating the conductivity, used as a synaptic weight to prevent sneak path current issues during synaptic operations. In this study, we fabricate a top-gated flash memory device based on two-dimensional (2D) materials, MoS2 and graphene, as a channel and a floating gate, respectively, and Al2O3 and HfO2 to increase the tunneling efficiency. We demonstrate the linear weight updates and repeatable characteristics of applying negative/positive pulses, and also emulate spike timing-dependent plasticity (STDP), one of the learning rules in a spiking neural network (SNN).

Tailoring the transfer characteristics and hysteresis in MoS2 transistors using substrate engineering

We demonstrate a novel form of transfer characteristics in substrate engineered MoS2 field effect transistors. Robust hysteresis with stable threshold voltages and a large gate voltage window is observed, which is suppressed at low temperatures. We analyse the dependence of the device characteristics on gate voltage range, gate stressing and sweep rates. We infer that the hysteresis originates from artificially created charged traps near the MoS2-SiO2 interface. These charge traps act as long range Coulomb scatterers and are screened at high carrier densities. The hysteresis is strongly suppressed in measurements on wafers devoid of the substrate treatment, providing a new extrinsic route to carefully tune the transfer characteristics.

Tunable and nonvolatile multibit data storage memory based on MoTe2/boron nitride/graphene heterostructures through contact engineering

Heterostructures formed by stacking atomically thin two-dimensional materials are promising candidates for flash memory devices to achieve premium performances, due to the capability of effective carrier modulation and unique charge trapping behavior at the interfaces with atomic flatness. Here, we report a nonvolatile floating-gate flash memory based on MoTe₂/h-BN/graphene van der Waals heterostructure, which possesses increased data storage capacity per cell and versatile tunability. The decent memory behavior of the device is enabled by the carriers stored in the floating gate of graphene layer, which tunnel through the dielectric layer of h-BN from the channel layer of MoTe₂ under static-electrical field. Consequently, the developed memory device is capable to store 2 bits per cell by applying varied gate bias to implement multi-distinctive current levels. The device also exhibits remarkable erase/program current ratio of ∼10⁵ with 1 µs switch speed and stable retention with estimated ∼30% charge loss after 10 yr. Furthermore, the memory device can operate in both p- and n-type modes through contact engineering, offering wide adaptability for emerging applications in electronic technologies, such as neuromorphic computing, data-adaptive energy efficient memory, and complex digital circuits.

Multi-level flash memory device based on stacked anisotropic ReS2-boron nitride-graphene heterostructures

Charge-trapping memory devices based on two-dimensional (2D) material heterostructures possess an atomically thin structure and excellent charge transport capability, making them promising candidates for next-generation flash memories to achieve miniaturized size, high storage capacity, fast switch speed, and low power consumption. Here, we report a nonvolatile floating-gate memory device based on an ReS₂/boron nitride/graphene heterostructure. The implemented ReS₂ memory device displays a large memory window exceeding 100 V, leading to an ultrahigh current ratio over 10⁸ between programming and erasing states. The ReS₂ memory device also exhibits an ultrafast switch speed of 1 μs. In addition, the device can endure hundreds of switching cycles and shows stable retention characteristics with ∼40% charge remaining after 10 years. More importantly, taking advantage of its anisotropic electrical properties, a single ReS₂ flake can achieve direction-sensitive multi-level data storage to enhance the data storage density. On the basis of these characteristics, the proposed ReS₂ memory device is potentially able to serve the entire memory device hierarchy, meeting the need for scalability, capacity, speed, retention, and endurance at each level.

Double-Gate MoS2 Field-Effect Transistor with a Multilayer Graphene Floating Gate: A Versatile Device for Logic, Memory, and Synaptic Applications

2D materials with low-temperature processing hold promise for electronic devices that augment conventional silicon technology. To meet this promise, devices should have capabilities not easily achieved with silicon technology, including planar fully-depleted silicon-on-insulator with substrate body-bias, or vertical finFETs with no body-bias capability. In this work, we fabricate and characterize a device [a double-gate MoS₂ field-effect transistor (FET) with hexagonal boron nitride (h-BN) gate dielectrics and a multi-layer graphene floating gate (FG)] in multiple operating conditions to demonstrate logic, memory, and synaptic applications; a range of h-BN thicknesses is investigated for charge retention in the FG. In particular, we demonstrate this device as a (i) logic FET with adjustable V_T by charges stored in the FG, (ii) digital flash memory with lower pass-through voltage to enable improved reliability, and (iii) synaptic device with decoupling of tunneling and gate dielectrics to achieve a symmetric program/erase conductance change. Overall, this versatile device, compatible to back-end-of-line integration, could readily augment silicon technology.

Comprehensive Performance Quasi-Non-Volatile Memory Compatible with Large-Scale Preparation by Chemical Vapor Deposition

Two-dimensional materials with atomic thickness have become candidates for wearable electronic devices in the future. Graphene and transition metal sulfides have received extensive attention in logic computing and sensing applications due to their lower power dissipation, so that their processes have been relatively mature for large-scale preparation. However, there are a few applications of two-dimensional materials in storage, which is not in line with the development trend of integration of storage and computing. Here, a charge storage quasi-non-volatile memory with a lanthanum incorporation high-k dielectric for next-generation memory devices is proposed. Thanks to the excellent electron capture capability of LaAlO₃, the MoS₂ memory exhibits a very comprehensive information storage capability, including robust endurance and ultra-fast write speed of 1 ms approximately. It is worth mentioning that it exhibits a long-term stable charge storage capacity (refresh time is about 1000 s), which is 10⁵ times that of the dynamic random access memory (refresh time is on a milliseconds timescale) so that the unnecessary power dissipation greatly reduces caused by frequent refresh. In addition, its simple manufacturing process makes it compatible with various current two-dimensional electronic devices, which will greatly promote the integration of two-dimensional electronic computing.

Native Oxide Seeded Spontaneous Integration of Dielectrics on Exfoliated Black Phosphorus

Two-dimensional (2D) semiconductors have been a central focus for next-generation electronics and optoelectronics owing to their great potential to extend the scaling limits in a silicon transistor. However, due to the lack of surface dangling bonds in most 2D semiconductors, such as graphene and transition metal dichalcogenides (TMDs), the direct growth of the high-κ film on these 2D materials via an atomic layer deposition (ALD) technique often produces dielectrics with poor quality, which hinders their integration in the modern semiconductor industry. Here, we comprehensively investigate the ALD growth of the Al₂O₃ layer on 2D exfoliated black phosphorus (BP). Intriguingly, we found that the 2D BP with "silicon-like" characteristics possesses a native surface oxide layer P_xO_y after air exposure. The P_xO_y-induced surface dangling bonds enable the spontaneous integration of the high-quality Al₂O₃ layer on the BP flake without any pretreatments to functionalize the surface. Additionally, the Al₂O₃ layer could effectively passivate BP to prevent its degradation in ambient conditions, which addresses the most serious problem of the BP material. Moreover, the Al₂O₃-encapsulated BP field-effect transistor (FET) exhibits good electrical transport performance, with a high hole mobility of ∼420 cm² V^-1 s^-1 and electron mobility of ∼80 cm² V^-1 s^-1. Moreover, the high-quality Al₂O₃ layer can also be integrated into the top-gated BP transistor and inverter. Our findings reveal the silicon-like characteristics of BP for the high-κ ALD dielectric growth technology, which promises the seamless integration of 2D BP in the modern semiconductor industry.

Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations

A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS₂ FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.

Reconfigurable Dipole-Induced Resistive Switching of MoS2 Thin Layers on Nb:SrTiO3

The controllable band gap and charge-trapping capability of MoS₂ render it suitable for use in the fabrication of various electrical devices with high-k dielectric oxides. In this study, we investigated reconfigurable resistance states in a MoS₂/Nb:SrTiO₃ heterostructure by using conductive atomic force microscopy. Low-resistance and high-resistance states were observed in all MoS₂ because of barrier height modification resulting from redistribution of charge and oxygen vacancies in the vicinity of interfaces. In a thin layer of the MoS₂ film, the carrier density was high, and layer-dependent transport properties appeared because of the charge separation in MoS₂. The hysteresis and switching voltage of the MoS₂/Nb:SrTiO₃ heterostructure could be varied by controlling the number of layers of MoS₂.

A non-volatile AND gate based on Al2O3/HfO2/Al2O3 charge-trap stack for in-situ storage applications

The emergence of two-dimensional (2D) materials has inspired academia in microelectronics to find a novel device structure to offer a potential technological route for increasing energy efficiency and processing speed for data storage and computing at transistor level. Devices based on 2D materials include logic gates and memories, each with their own unique features. However, integrating logic function and memory into a single device has barely been studied. Here, we report a non-volatile AND gate based on Al₂O₃/HfO₂/Al₂O₃ charge-trap stack. The device can store charges after completing logic operation. The ratio of high and low current states during logic operations can exceed 10⁵. The output current states during the logic and memory operations still have a two orders of magnitude distinction after 800 s, indicating that this device possesses the non-volatile characteristic. The device has potential applications for in-situ memory applications, which makes it a possible candidate to break the "memory wall" at transistor level.