High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA

Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse, 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability that allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGAs provide the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify that the image quality was not compromised for speed.

FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications

Miniaturized calcium imaging is an emerging neural recording technique that has been widely used for monitoring neural activity on a large scale at a specific brain region of rats or mice. Most existing calcium-image analysis pipelines operate offline. This results in long processing latency, making it difficult to realize closed-loop feedback stimulation for brain research. In recent work, we have proposed an FPGA-based real-time calcium image processing pipeline for closed-loop feedback applications. It can perform real-time calcium image motion correction, enhancement, fast trace extraction, and real-time decoding from extracted traces. Here, we extend this work by proposing a variety of neural network based methods for real-time decoding and evaluate the tradeoff among these decoding methods and accelerator designs. We introduce the implementation of the neural network based decoders on the FPGA, and show their speedup against the implementation on the ARM processor. Our FPGA implementation enables the real-time calcium image decoding with sub-ms processing latency for closed-loop feedback applications.

A Neuromorphic Proto-Object Based Dynamic Visual Saliency Model With a Hybrid FPGA Implementation

Computing and attending to salient regions of a visual scene is an innate and necessary preprocessing step for both biological and engineered systems performing high-level visual tasks including object detection, tracking, and classification. Computational bandwidth and speed are improved by preferentially devoting computational resources to salient regions of the visual field. The human brain computes saliency effortlessly, but modeling this task in engineered systems is challenging. We first present a neuromorphic dynamic saliency model, which is bottom-up, feed-forward, and based on the notion of proto-objects with neurophysiological spatio-temporal features requiring no training. Our neuromorphic model outperforms state-of-the-art dynamic visual saliency models in predicting human eye fixations (i.e., ground truth saliency). Secondly, we present a hybrid FPGA implementation of the model for real-time applications, capable of processing 112×84 resolution frames at 18.71 Hz running at a 100 MHz clock rate - a 23.77× speedup from the software implementation. Additionally, our fixed-point model of the FPGA implementation yields comparable results to the software implementation.

Improving an open-source commercial system to reliably perform activity-dependent stimulation

OBJECTIVE

Activity-dependent stimulation (ADS) is designed to strengthen the connections between neuronal circuits and therefore may be a promising tool for promoting neurophysiological reorganization following a brain injury. To successfully perform this technique, two criteria must be met: (1) spikes in the extracellular electrical field potential must be detected accurately at one site of interest, and (2) stimulation pulses generated at fixed (<1 ms jitter), low-latency (<10 ms) intervals relative to each detected spike must be delivered reliably to a second site of interest. Here, we aimed to improve noise rejection in a low-cost commercial system to reliably perform ADS in awake, behaving rats, while maintaining latency requirements.

APPROACH

We implemented a spike detection state machine on a field-programmable gate array (FPGA). Because the accuracy of spike detection can be heavily reduced in awake and behaving animals due to biological artifacts such as movement and chewing, the state machine tracks candidate spike waveforms, checking them against multiple programmable thresholds and rejecting any spikes that fail to meet a programmed threshold criterion.

MAIN RESULTS

A series of offline analyses showed that our implementation was able to appropriately trigger stimulation during epochs of biological artifacts with an overall accuracy between 72% and 97%, fixed computational latency of 167 µs, and an algorithmic latency of 300 µs to 800 µs.

SIGNIFICANCE

Our improvements have been made open-source and are freely available to all scientists working on closed-loop neuroprosthetic devices. Importantly, the improvements are easily incorporated into existing workflows that utilize the Intan Stimulation and Recording Controller.

An FPGA-Based Backend System for Intravascular Photoacoustic and Ultrasound Imaging

The integration of intravascular ultrasound (IVUS) and intravascular photoacoustic (IVPA) imaging produces an imaging modality with high sensitivity and specificity which is particularly needed in interventional cardiology. Conventional side-looking IVUS imaging with a single-element ultrasound (US) transducer lacks forward-viewing capability, which limits the application of this imaging mode in intravascular intervention guidance, Doppler-based flow measurement, and visualization of nearly, or totally blocked arteries. For both side-looking and forward-looking imaging, the necessity to mechanically scan the US transducer limits the imaging frame rate, and therefore, array-based solutions are desired. In this paper, we present a low-cost, compact, high-speed, and programmable imaging system based on a field-programmable gate array suitable for dual-mode forward-looking IVUS/IVPA imaging. The system has 16 US transmit and receive channels and functions in multiple modes including interleaved photoacoustic (PA) and US imaging, hardware-based high-frame-rate US imaging, software-driven US imaging, and velocity measurement. The system is implemented in the register-transfer level, and the central system controller is implemented as a finite-state machine. The system was tested with a capacitive micromachined ultrasonic transducer array. A 170-frames-per-second (FPS) US imaging frame rate is achieved in the hardware-based high-frame-rate US imaging mode while the interleaved PA and US imaging mode operates at a 60-FPS US and a laser-limited 20-FPS PA imaging frame rate. The performance of the system benefits from the flexibility and efficiency provided by the low-level implementation. The resulting system provides a convenient backend platform for research and clinical IVPA and IVUS imaging.

FPGA-based RF interference reduction techniques for simultaneous PET-MRI

The combination of positron emission tomography (PET) and magnetic resonance imaging (MRI) as a multi-modal imaging technique is considered very promising and powerful with regard to in vivo disease progression examination, therapy response monitoring and drug development. However, PET-MRI system design enabling simultaneous operation with unaffected intrinsic performance of both modalities is challenging. As one of the major issues, both the PET detectors and the MRI radio-frequency (RF) subsystem are exposed to electromagnetic (EM) interference, which may lead to PET and MRI signal-to-noise ratio (SNR) deteriorations. Early digitization of electronic PET signals within the MRI bore helps to preserve PET SNR, but occurs at the expense of increased amount of PET electronics inside the MRI and associated RF field emissions. This raises the likelihood of PET-related MRI interference by coupling into the MRI RF coil unwanted spurious signals considered as RF noise, as it degrades MRI SNR and results in MR image artefacts. RF shielding of PET detectors is a commonly used technique to reduce PET-related RF interferences, but can introduce eddy-current-related MRI disturbances and hinder the highest system integration. In this paper, we present RF interference reduction methods which rely on EM field coupling-decoupling principles of RF receive coils rather than suppressing emitted fields. By modifying clock frequencies and changing clock phase relations of digital circuits, the resulting RF field emission is optimised with regard to a lower field coupling into the MRI RF coil, thereby increasing the RF silence of PET detectors. Our methods are demonstrated by performing FPGA-based clock frequency and phase shifting of digital silicon photo-multipliers (dSiPMs) used in the PET modules of our MR-compatible Hyperion II (D) PET insert. We present simulations and magnetic-field map scans visualising the impact of altered clock phase pattern on the spatial RF field distribution, followed by MRI noise and SNR scans performed with an operating PET module using different clock frequencies and phase patterns. The methods were implemented via firmware design changes without any hardware modifications. This introduces new means of flexibility by enabling adaptive RF interference reduction optimisations in the field, e.g. when using a PET insert with different MRI systems or when different MRI RF coil types are to be operated with the same PET detector.

Study on a real-time BEAM system for diagnosis assistance based on a system on chips design

As an innovative as well as an interdisciplinary research project, this study performed an analysis of brain signals so as to establish BrainIC as an auxiliary tool for physician diagnosis. Cognition behavior sciences, embedded technology, system on chips (SOC) design and physiological signal processing are integrated in this work. Moreover, a chip is built for real-time electroencephalography (EEG) processing purposes and a Brain Electrical Activity Mapping (BEAM) system, and a knowledge database is constructed to diagnose psychosis and body challenges in learning various behaviors and signals antithesis by a fuzzy inference engine. This work is completed with a medical support system developed for the mentally disabled or the elderly abled.

Hardware accelerated compression of LIDAR data using FPGA devices

Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load.

Development of a 64 channel ultrasonic high frequency linear array imaging system

In order to improve the lateral resolution and extend the field of view of a previously reported 48 element 30 MHz ultrasound linear array and 16-channel digital imaging system, the development of a 256 element 30 MHz linear array and an ultrasound imaging system with increased channel count has been undertaken. This paper reports the design and testing of a 64 channel digital imaging system which consists of an analog front-end pulser/receiver, 64 channels of Time-Gain Compensation (TGC), 64 channels of high-speed digitizer as well as a beamformer. A Personal Computer (PC) is used as the user interface to display real-time images. This system is designed as a platform for the purpose of testing the performance of high frequency linear arrays that have been developed in house. Therefore conventional approaches were taken it its implementation. Flexibility and ease of use are of primary concern whereas consideration of cost-effectiveness and novelty in design are only secondary. Even so, there are many issues at higher frequencies but do not exist at lower frequencies need to be solved. The system provides 64 channels of excitation pulsers while receiving simultaneously at a 20-120 MHz sampling rate to 12-bits. The digitized data from all channels are first fed through Field Programmable Gate Arrays (FPGAs), and then stored in memories. These raw data are accessed by the beamforming processor to re-build the image or to be downloaded to the PC for further processing. The beamformer that applies delays to the echoes of each channel is implemented with the strategy that combines coarse (8.3 ns) and fine delays (2 ns). The coarse delays are integer multiples of the sampling clock rate and are achieved by controlling the write enable pin of the First-In-First-Out (FIFO) memory to obtain valid beamforming data. The fine delays are accomplished with interpolation filters. This system is capable of achieving a maximum frame rate of 50 frames per second. Wire phantom images acquired with this system show a spatial resolution of 146 μm (lateral) and 54 μm (axial). Images with excised rabbit and pig eyeball as well as mouse embryo were also acquired to demonstrate its imaging capability.

A New Statistics-Based Online Baseline Restorer for a High Count-Rate Fully Digital System

The goal of this work is to develop a novel, accurate, real-time digital baseline restorer using online statistical processing for a high count-rate digital system such as positron emission tomography (PET). In high count-rate nuclear instrumentation applications, analog signals are DC-coupled for better performance. However, the detectors, pre-amplifiers and other front-end electronics would cause a signal baseline drift in a DC-coupling system, which will degrade the performance of energy resolution and positioning accuracy. Event pileups normally exist in a high-count rate system and the baseline drift will create errors in the event pileup-correction. Hence, a baseline restorer (BLR) is required in a high count-rate system to remove the DC drift ahead of the pileup correction. Many methods have been reported for BLR from classic analog methods to digital filter solutions. However a single channel BLR with analog method can only work under 500 kcps count-rate, and normally an analog front-end application-specific integrated circuits (ASIC) is required for the application involved hundreds BLR such as a PET camera. We have developed a simple statistics-based online baseline restorer (SOBLR) for a high count-rate fully digital system. In this method, we acquire additional samples, excluding the real gamma pulses, from the existing free-running ADC in the digital system, and perform online statistical processing to generate a baseline value. This baseline value will be subtracted from the digitized waveform to retrieve its original pulse with zero-baseline drift. This method can self-track the baseline without a micro-controller involved. The circuit consists of two digital counter/timers, one comparator, one register and one subtraction unit. Simulation shows a single channel works at 30 Mcps count-rate with pileup condition. 336 baseline restorer circuits have been implemented into 12 field-programmable-gate-arrays (FPGA) for our new fully digital PET system.

Detection and Processing Techniques of FECG Signal for Fetal Monitoring

Fetal electrocardiogram (FECG) signal contains potentially precise information that could assist clinicians in making more appropriate and timely decisions during labor. The ultimate reason for the interest in FECG signal analysis is in clinical diagnosis and biomedical applications. The extraction and detection of the FECG signal from composite abdominal signals with powerful and advance methodologies are becoming very important requirements in fetal monitoring. The purpose of this review paper is to illustrate the various methodologies and developed algorithms on FECG signal detection and analysis to provide efficient and effective ways of understanding the FECG signal and its nature for fetal monitoring. A comparative study has been carried out to show the performance and accuracy of various methods of FECG signal analysis for fetal monitoring. Finally, this paper further focused some of the hardware implementations using electrical signals for monitoring the fetal heart rate. This paper opens up a passage for researchers, physicians, and end users to advocate an excellent understanding of FECG signal and its analysis procedures for fetal heart rate monitoring system.

FPGA-Based Front-End Electronics for Positron Emission Tomography

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.

Integration of digital signal processing technologies with pulsed electron paramagnetic resonance imaging

The integration of modern data acquisition and digital signal processing (DSP) technologies with Fourier transform electron paramagnetic resonance (FT-EPR) imaging at radiofrequencies (RF) is described. The FT-EPR system operates at a Larmor frequency (L(f)) of 300MHz to facilitate in vivo studies. This relatively low frequency L(f), in conjunction with our approximately 10MHz signal bandwidth, enables the use of direct free induction decay time-locked subsampling (TLSS). This particular technique provides advantages by eliminating the traditional analog intermediate frequency downconversion stage along with the corresponding noise sources. TLSS also results in manageable sample rates that facilitate the design of DSP-based data acquisition and image processing platforms. More specifically, we utilize a high-speed field programmable gate array (FPGA) and a DSP processor to perform advanced real-time signal and image processing. The migration to a DSP-based configuration offers the benefits of improved EPR system performance, as well as increased adaptability to various EPR system configurations (i.e., software configurable systems instead of hardware reconfigurations). The required modifications to the FT-EPR system design are described, with focus on the addition of DSP technologies including the application-specific hardware, software, and firmware developed for the FPGA and DSP processor. The first results of using real-time DSP technologies in conjunction with direct detection bandpass sampling to implement EPR imaging at RF frequencies are presented.