CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Limitations and Drawbacks of DQE Estimation Methods Applied to Electron Detectors

The DQE is generally accepted as the main figure of merit for the comparison between electron detectors, and most of the time given as a unique number at the Nyquist frequency while it is known to vary with electron dose. It is usually estimated thanks to a method improved by McMullan in 2009. The purpose of this work is to analyse and to criticize this DQE extraction method on the basis of measurement and model results, and to give recommendations for fair comparison between detectors, wondering if the DQE is the right figure of merit for electron detectors.

New structure transistors for advanced technology node CMOS ICs

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to three-dimensional (3D) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs (CFET), 3D stack (3DS) FETs and vertical-channel transistors (VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

Enhancement-Mode Ambipolar Thin-Film Transistors and CMOS Logic Circuits using Bilayer Ga2O3/NiO Semiconductors

Recent advancements in power electronics have been driven by Ga2O3-based ultrawide bandgap (UWBG) semiconductor devices, enabling efficient high-current switching. However, integrating Ga2O3 power devices with essential silicon CMOS logic circuits for advanced control poses fabrication challenges. Researchers have introduced Ga2O3-based NMOS and pseudo-CMOS circuits for integration, but these circuits may either consume more power or increase the design complexity. Hence, this article proposes Ga2O3-based CMOS realized using heterogeneous 3D-stacked bilayer ambipolar transistors. These ambipolar transistors consist of HfO2/NiO/Ga2O3/NiO/HfO2 heterostructures that are wrapped around by the Ti/Au gate electrode, resulting in record high electron and hole current on/off ratios of 109 and 107. The threshold voltage, subthreshold swing, and current density measured from 100 ambipolar devices (across 5 batches) are around -7.99 ± 0.92 V (p-channel) and 7.81 ± 0.81 V (n-channel), 0.59 ± 0.07 V/dec (p-channel) and 0.61 ± 0.06 V/dec (n-channel), and 0.99 ± 0.26 mA/mm (p-channel) and 58.23 ± 12.99 mA/mm (n-channel), respectively. All the 100 ambipolar devices showed decent long-term stability over a period of 200 days, exhibiting reliable electrical performance. The threshold voltage shift (ΔVTH) after negative bias stressing for a period of 3500 s is around 11.52 V (p-channel) and 10.21 V (n-channel), respectively. Notably, the n-channels exhibit ∼2 orders higher on/off ratio than the best Ga2O3 unipolar transistors at 300 °C. Moreover, the polarities of ambipolar transistors are reconfigurable into p- or n-MOS, which are integrated to demonstrate CMOS inverter, NOR, and NAND logic gates. The switching periods from "0" to "1" and from "1" to "0" of NOR are 0.12 and 0.17 μs, and those of NAND are 0.16 and 0.13 μs. This work lays the foundation of oxide-semiconductor-based CMOS for future integrated electronics.

Investigation and Modeling of the Behavior of Temperature Characteristics of 0.3-1.1 GHz Complementary Metal Oxide Semiconductor Class-A Broadband Power Amplifiers

A power amplifier (PA) stands as a central module within the electronic information system (EIS), and any variation in a PA's specifications has a direct impact on the EIS's performance, especially in the face of temperature fluctuations. In examining the influence of PA specification changes on the EIS, we employed support vector machine (SVM) to model the behavior of the temperature characteristics of 0.3-1.1 GHz complementary metal oxide semiconductor (CMOS) class-A broadband PAs. The results show that the parameters of S11, S12, S21, and S22 can be effectively modeled. SVM outperforms Elman and GRNN in terms of combined modeling time and modeling accuracy. This research can be extended to modeling the behavior of other types of power amplifiers or devices and circuits.

A Multidisciplinary Approach toward CMOS Capacitive Sensor Array for Droplet Analysis

This paper introduces an innovative method for the analysis of alcohol-water droplets on a CMOS capacitive sensor, leveraging the controlled thermal behavior of the droplets. Using this sensing method, the capacitive sensor measures the total time of evaporation (ToE), which can be influenced by the droplet volume, temperature, and chemical composition. We explored this sensing method by introducing binary mixtures of water and ethanol or methanol across a range of concentrations (0-100%, with 10% increments). The experimental results indicate that while the capacitive sensor is effective in measuring both the total ToE and dielectric properties, a higher dynamic range and resolution are observed in the former. Additionally, an array of sensing electrodes successfully monitors the droplet-sensor surface interaction. However practical considerations such as the creation of parasitic capacitance due to mismatch, arise from the large sensing area in the proposed capacitive sensors and other similar devices. In this paper, we discuss this non-ideality and propose a solution. Also, this paper showcases the benefits of utilizing a CMOS capacitive sensing method for accurately measuring ToE.

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying -45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

Preliminary Characterization of an Active CMOS Pad Detector for Tracking and Dosimetry in HDR Brachytherapy

We assessed the accuracy of a prototype radiation detector with a built in CMOS amplifier for use in dosimetry for high dose rate brachytherapy. The detectors were fabricated on two substrates of epitaxial high resistivity silicon. The radiation detection performance of prototypes has been tested by ion beam induced charge (IBIC) microscopy using a 5.5 MeV alpha particle microbeam. We also carried out the HDR Ir-192 radiation source tracking at different depths and angular dose dependence in a water equivalent phantom. The detectors show sensitivities spanning from (5.8 ± 0.021) × 10-8 to (3.6 ± 0.14) × 10-8 nC Gy-1 mCi-1 mm-2. The depth variation of the dose is within 5% with that calculated by TG-43. Higher discrepancies are recorded for 2 mm and 7 mm depths due to the scattering of secondary particles and the perturbation of the radiation field induced in the ceramic/golden package. Dwell positions and dwell time are reconstructed within ±1 mm and 20 ms, respectively. The prototype detectors provide an unprecedented sensitivity thanks to its monolithic amplification stage. Future investigation of this technology will include the optimisation of the packaging technique.

High-resolution X-Ray imaging of small animal samples based on Commercial-Off-The-Shelf CMOS image sensors

 An automated system for acquiring microscopic-resolution radiographic images of biological samples was developed. Mass-produced, low-cost, and easily automated components were used, such as Commercial-Off-The-Self CMOS image sensors (CIS), stepper motors, and control boards based on Arduino and RaspberryPi. System configuration, imaging protocols, and Image processing (filtering and stitching) were defined to obtain high-resolution images and for successful computational image reconstruction. Radiographic images were obtained for animal samples including the widely used animal models zebrafish (Danio rerio) and the fruit-fly (Drosophila melanogaster), as well as other small animal samples. The use of phosphotungstic acid (PTA) as a contrast agent was also studied. Radiographic images with resolutions of up to (7±0.6)μm were obtained, making this system comparable to commercial ones. This work constitutes a starting point for the development of more complex systems such as X-ray attenuation micro-tomography systems based on low-cost off-the-shelf technology. It will also bring the possibility to expand the studies that can be carried out with small animal models at many institutions (mostly those working on tight budgets), particularly those on the effects of ionizing radiation and absorption of heavy metal contaminants in animal tissues.

Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found.

Single-Grating Monolithic Spatial Heterodyne Raman Spectrometer: An Investigation on the Effects of Detector Selection

Spatial heterodyne Raman spectrometers (SHRSs) are modified forms of Michelson interferometers, except the mirrors in a Michelson interferometer are replaced with stationary diffraction gratings. This design removes the need for an entrance slit, as is the case in a dispersive spectrometer, and removes the need to scan the spectrum by using a moving mirror in a modern Michelson interferometer. In previous studies, various SHRS variants, such as free-standing two-grating SHRS, single-grating SHRS (1g-SHRS), monolithic SHRS (mSHRS), and single-grating mSHRS (1g-mSHRS), have been evaluated. However, the present study exclusively focuses on the 1g-mSHRS configuration. The 1g-mSHRS and 1g-SHRS increase the spectral range at fixed grating line density while trading off spectral resolution and resolving power. The mSHRS benefits from increased rigidity, lack of moving parts, and reduced footprint. In this study, we investigate how the choice of detector impacts the performance of the 1g-mSHRS system, with a specific focus on evaluating the performance of three types of cameras: charged-coupled device (CCD), intensified CCD (ICCD), and complementary metal-oxide-semiconductor (CMOS) cameras. These systems were evaluated using geological, organic, and inorganic samples using a 532 nm continuous wave laser for the CMOS and CCD cameras, and a 532 nm neodymium-doped yttrium aluminum garnet pulsed laser for the ICCD camera. The footprint of the 1g-mSHRS was 3.5 × 3.5 × 2.5 cm3 with a mass of 272 g or 80 g, depending on whether the monolith housing is included or not. We found that increasing the number of pixels utilized along the x-axis of the camera increases fringe visibility (FV) and optimizes the resolution (by capturing the entirety of the grating and magnifying the fringes). The number of pixels utilized in the y-axis, chip size, and dimensions, affect the signal-to-noise ratio of the systems. Additionally, we discuss the effect of pixel pitch on the recovery of Fizeau fringes, including the relationship between the Nyquist frequency, aliasing, and FV.

High-Performance Complementary Circuits from Two-Dimensional MoTe2

Two-dimensional (2D) materials hold great promise for future complementary metal-oxide semiconductor (CMOS) technology. However, the lack of effective methods to tune the Schottky barrier poses a challenge in constructing high-performance complementary circuits from the same material. Here, we reveal that the polarity of pristine MoTe2 field-effect transistors (FETs) with minimized air exposure is n-type, irrespective of the metal contact type. The fabricated n-FETs with palladium contact can reach electron currents up to 275 μA/μm at VDS = 2 V. For p-FETs, we introduce a novel nitric oxide doping strategy, allowing a controlled transition of MoTe2 FETs from n-type to unipolar p-type. By doping only in the contact region, we demonstrate hole currents up to 170 μA/μm at VDS= -2 V with preserved Ion/Ioff ratios of 105. Finally, we present a complementary inverter circuit comprising the high-performance n- and p-type FETs based on MoTe2, promoting the application of 2D materials in future electronic systems.

Metal Microelectromechanical Resonator Exhibiting Fast Human Activity Detection

This work presents a MEMS resonator used as an ultra-high resolution water vapor sensor (humidity sensing) to detect human activity through finger movement as a demonstrator example. This microelectromechanical resonator is designed as a clamped-clamped beam fabricated using the top metal layer of a commercial CMOS technology (0.35 μm CMOS-AMS) and monolithically integrated with conditioning and readout circuitry. Sensing is performed through the resonance frequency change due to the addition of water onto the clamped-clamped beam coming from the moisture created by the evaporation of water in the human body. The sensitivity and high-speed response to the addition of water onto the metal bridge, as well as the quick dewetting of the surface, make it suitable for low-power human activity sensing.

A Synthetic Ultra-Wideband Transceiver for Millimeter-Wave Imaging Applications

In this work, we present a transceiver front-end in SiGe BiCMOS technology that can provide an ultra-wide bandwidth of 100 GHz at millimeter-wave frequencies. The front-end utilizes an innovative arrangement to efficiently distribute broadband-generated pulses and coherently combine received pulses with minimal loss. This leads to the realization of a fully integrated ultra-high-resolution imaging chip for biomedical applications. We realized an ultra-wide imaging band-width of 100 GHz via the integration of two adjacent disjointed frequency sub-bands of 10-50 GHz and 50-110 GHz. The transceiver front-end is capable of both transmit (TX) and receive (RX) operations. This is a crucial component for a system that can be expanded by repeating a single unit cell in both the horizontal and vertical directions. The imaging elements were designed and fabricated in Global Foundry 130-nm SiGe 8XP process technology.

Fabrication and Characterization of Photovoltaic Microgenerators Using the Complementary Metal Oxide Semiconductor Process

This study develops a photovoltaic microgenerator based on the complementary metal oxide semiconductor (CMOS) process. The photovoltaic microgenerator converts the absorbed light energy into electrical energy using the photovoltaic effect. The material for the photovoltaic microgenerator is silicon, and its structure consists of patterned p-n junctions. The design of the photovoltaic microgenerator utilizes a grid-like shape, forming a large-area p-n junction with a patterned p-doping and N-well structure to enhance the photocurrent and improve the device's performance. The photovoltaic microgenerator is fabricated employing the CMOS process with post-processing step. Post-processing is applied to enhance the microgenerator's light absorption and energy-conversion efficiency. This involves using wet etching with buffered-oxide etch (BOE) to remove the silicon dioxide layer above the p-n junctions, allowing direct illumination of the p-n junctions. The area of the photovoltaic microgenerator is 0.79 mm2. The experimental results show that under an illumination intensity of 1000 W/m2, the photovoltaic microgenerator exhibits an open-circuit voltage of 0.53 V, a short-circuit current of 233 µA, a maximum output power of 99 µW, a fill factor of 0.8, and an energy-conversion efficiency of 12.5%.

Microscale 3-D Capacitance Tomography with a CMOS Sensor Array

Electrical capacitance tomography (ECT) is a non-optical imaging technique in which a map of the interior permittivity of a volume is estimated by making capacitance measurements at its boundary and solving an inverse problem. While previous ECT demonstrations have often been at centimeter scales, ECT is not limited to macroscopic systems. In this paper, we demonstrate ECT imaging of polymer microspheres and bacterial biofilms using a CMOS microelectrode array, achieving spatial resolution of 10 microns. Additionally, we propose a deep learning architecture and an improved multi-objective training scheme for reconstructing out-of-plane permittivity maps from the sensor measurements. Experimental results show that the proposed approach is able to resolve microscopic 3-D structures, achieving 91.5% prediction accuracy on the microsphere dataset and 82.7% on the biofilm dataset, including an average of 4.6% improvement over baseline computational methods.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

A 54 µW CMOS Auto-Trimming Bandgap References (ATBGR) Achieving 90 dB PSRR for Artificial Intelligence of Things (AIoT) Chips

An Auto-Trimming CMOS Bandgap References Circuit (ATBGR) with PSRR enhancement circuit for Artificial Intelligence of Things (AIoT) chips is presented in this paper. The ATBGR is designed with a first-order temperature compensation technique providing a stable reference voltage of 1.25 V in the ranges of input voltages from 1.65 V to 4.5 V. An auto-trimming circuit is integrated into a PTAT resistor of BGR to minimize the influences of the process variations. The four parallel resistor pairs with PMOS switches are connected in series with the PTAT resistor. The reference voltage, VREF, is compared to an external constant value, 1.25 V, through an operational amplifier, and the output of the de-multiplexer is used to configure the PMOS switches. High power supply rejection is achieved through a PSRR enhancement circuit constituting a cascaded PMOS common gate pair. The ATBGR circuit is fabricated in 180 nm CMOS technology, consuming an area of 0.03277 mm2. The auto-trimming method yields an average temperature coefficient of 9.99 ppm/°C with temperature ranges from -40 °C to 125 °C, and a power supply rejection ratio of -90 dB at 100 MHz is obtained. The line regulation of the proposed circuit is 0.434%/V with power consumption of 54.12 µW at room temperature.

"GeSn Rule-23"-The Performance Limit of GeSn Infrared Photodiodes

Group-IV GeSn photodetectors (PDs) compatible with standard complementary metal-oxide-semiconductor (CMOS) processing have emerged as a new and non-toxic infrared detection technology to enable a wide range of infrared applications. The performance of GeSn PDs is highly dependent on the Sn composition and operation temperature. Here, we develop theoretical models to establish a simple rule of thumb, namely "GeSn-rule 23", to describe GeSn PDs' dark current density in terms of operation temperature, cutoff wavelength, and Sn composition. In addition, analysis of GeSn PDs' performance shows that the responsivity, detectivity, and bandwidth are highly dependent on operation temperature. This rule provides a simple and convenient indicator for device developers to estimate the device performance at various conditions for practical applications.

A State-of-the-Art Review on CMOS Radio Frequency Power Amplifiers for Wireless Communication Systems

Wireless communication systems have undergone significant development in recent years, particularly with the transition from fourth generation (4G) to fifth generation (5G). As the number of wireless devices and mobile data usage increase, there is a growing need for enhancements and upgrades to the current wireless communication systems. CMOS transceivers are increasingly being explored to meet the requirements of the latest wireless communication protocols and applications while achieving the goal of system-on-chip (SoC). The radio frequency power amplifier (RFPA) in a CMOS transmitter plays a crucial role in amplifying RF signals and transmitting them from the antenna. This state-of-the-art review paper presents a concise discussion of the performance metrics that are important for designing a CMOS PA, followed by an overview of the trending research on CMOS PA techniques that focuses on efficiency, linearity, and bandwidth enhancement.

An Ultra-Low-Power Analog Multiplier-Divider Compatible with Digital Code for RRAM-Based Computing-in-Memory Macros

This manuscript presents an ultra-low-power analog multiplier-divider compatible with digital code words, which is applicable to the integrated structure of resistive random-access memory (RRAM)-based computing-in-memory (CIM) macros. Current multiplication and division are accomplished by a current-mirror-based structure. Compared with digital dividers to achieve higher precision and operation speed, analog dividers present the advantages of a reduced power consumption and a simple circuit structure in lower precision operations, thus improving the energy efficiency. Designed and fabricated in a 55 nm CMOS process, the proposed work is capable of achieving 8-bit precision for analog current multiplication and division operations. Measurement results show that the signal delay is 1 μs when performing 8-bit operation, with a bandwidth of 1.4 MHz. The power consumption is less than 6.15 μW with a 1.2 V supply voltage. The proposed multiplier-divider can increase the operation capacity by dividing the input current and digital code while reducing the power consumption and complexity required by division, which can be further utilized in real-time operation of edge computing devices.

A Compact and Low-Power SoC Design for Spiking Neural Network Based on Current Multiplier Charge Injector Synapse

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and circuit designs. In this work, the SNN has been constituted from the analog neuron and synaptic circuits, which are designed to optimize both the chip area and power consumption. The proposed synapse circuit is based on a current multiplier charge injector (CMCI) circuit, which can significantly reduce power consumption and chip area compared with the previous work while allowing for design scalability for higher resolutions. The proposed neuron circuit employs an asynchronous structure, which makes it highly sensitive to input synaptic currents and enables it to achieve higher energy efficiency. To compare the performance of the proposed SoC in its area and power consumption, we implemented a digital SoC for the same SNN model in FPGA. The proposed SNN chip, when trained using the MNIST dataset, achieves a classification accuracy of 96.56%. The presented SNN chip has been implemented using a 65 nm CMOS process for fabrication. The entire chip occupies 0.96 mm2 and consumes an average power of 530 μW, which is 200 times lower than its digital counterpart.

A Multimode 28 GHz CMOS Fully Differential Beamforming IC for Phased Array Transceivers

A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and beam pattern. The BFIC has eight differential beamforming channels each consisting of the two-stage bi-directional amplifier with a precise gain control circuit, a six-bit phase shifter, a three-bit digital step attenuator, and a tuning bit for amplitude and phase variation compensation. The Tx and Rx mode overall gains of the differential eight-channel BFIC are around 11 dB and 9 dB, respectively, at 27.0-29.5 GHz. The return losses of the Tx mode and Rx mode are >10 dB at 27.0-29.5 GHz. The maximum phase of 354° with a phase resolution of 5.6° and the maximum attenuation of 31 dB, including the gain control bits with an attenuation resolution of 1 dB, is achieved at 27.0-29.5 GHz. The root mean square (RMS) phase and amplitude errors are <3.2° and <0.6 dB at 27.0-29.5 GHz, respectively. The chip size is 3.0 × 3.5 mm², including pads, and Tx mode current consumption is 580 mA at 2.5 V supply voltage.

Exploring the Potential of Broadband Complementary Metal Oxide Semiconductor Micro-Coil Nuclear Magnetic Resonance for Environmental Research

With sensitivity being the Achilles' heel of nuclear magnetic resonance (NMR), the superior mass sensitivity offered by micro-coils can be an excellent choice for tiny, mass limited samples such as eggs and small organisms. Recently, complementary metal oxide semiconductor (CMOS)-based micro-coil transceivers have been reported and demonstrate excellent mass sensitivity. However, the ability of broadband CMOS micro-coils to study heteronuclei has yet to be investigated, and here their potential is explored within the lens of environmental research. Eleven nuclei including 7Li, 19F, 31P and, 205Tl were studied and detection limits in the low to mid picomole range were found for an extended experiment. Further, two environmentally relevant samples (a sprouting broccoli seed and a D. magna egg) were successfully studied using the CMOS micro-coil system. 13C NMR was used to help resolve broad signals in the 1H spectrum of the 13C enriched broccoli seed, and steady state free precession was used to improve the signal-to-noise ratio by a factor of six. 19F NMR was used to track fluorinated contaminants in a single D. magna egg, showing potential for studying egg-pollutant interactions. Overall, CMOS micro-coil NMR demonstrates significant promise in environmental research, especially when the future potential to scale to multiple coil arrays (greatly improving throughput) is considered.