An unsupervised real-time spike sorting system based on optimized OSort

Objective. The OSort algorithm, a pivotal unsupervised spike sorting method, has been implemented in dedicated hardware devices for real-time spike sorting. However, due to the inherent complexity of neural recording environments, OSort still grapples with numerous transient cluster occurrences during the practical sorting process. This leads to substantial memory usage, heavy computational load, and complex hardware architectures, especially in noisy recordings and multi-channel systems.Approach. This study introduces an optimized OSort algorithm (opt-OSort) which utilizes correlation coefficient (CC), instead of Euclidean distance as classification criterion. TheCCmethod not only bolsters the robustness of spike classification amidst the diverse and ever-changing conditions of physiological and recording noise environments, but also can finish the entire sorting procedure within a fixed number of cluster slots, thus preventing a large number of transient clusters. Moreover, the opt-OSort incorporates two configurable validation loops to efficiently reject cluster outliers and track recording variations caused by electrode drifting in real-time.Main results. The opt-OSort significantly reduces transient cluster occurrences by two orders of magnitude and decreases memory usage by 2.5-80 times in the number of pre-allocated transient clusters compared with other hardware implementations of OSort. The opt-OSort maintains an accuracy comparable to offline OSort and other commonly-used algorithms, with a sorting time of 0.68µs as measured by the hardware-implemented system in both simulated datasets and experimental data. The opt-OSort's ability to handle variations in neural activity caused by electrode drifting is also demonstrated.Significance. These results present a rapid, precise, and robust spike sorting solution suitable for integration into low-power, portable, closed-loop neural control systems and brain-computer interfaces.

A Five-Channel Weighted Real-Time Algorithm for High-Density Electrodes Spike Sorting

With the application of high-density neural probes, a neuron can be detected by multiple adjacent probes, and the traditional single-channel spike sorting is no longer suitable. In this paper, we propose a five-channel weighted real-time spike sorting algorithm based on template-matching to process neural signals recorded by high-density probes. This work uses the signals of the center channel and the adjacent four channels to form a five-channel template by weighting, and employs a modified OSort algorithm with unsupervised learning to update the template. We implemented automatic online spike sorting, and tested it with both ground truth recordings and simulated datasets. The experiments show that our algorithm utilizing the information of adjacent channels has a higher sorting accuracy than traditional single-channel spike sorting. The average sorting accuracy reaches 89%, compared to 78% for single-channel.

Large-scale, closed-loop interrogation of neural circuits underlying cognition

Cognitive functions are increasingly understood to involve coordinated activity patterns between multiple brain regions, and their disruption by neuropsychiatric disorders is similarly complex. Closed-loop neurostimulation can directly modulate neural signals with temporal and spatial precision. How to leverage such an approach to effectively identify and target distributed neural networks implicated in mediating cognition remains unclear. We review current conceptual and technical advances in this area, proposing that devices that enable large-scale acquisition, integrated processing, and multiregion, arbitrary waveform stimulation will be critical for mechanistically driven manipulation of cognitive processes in physiological and pathological brain networks.

Neuromorphic-Based Neuroprostheses for Brain Rewiring: State-of-the-Art and Perspectives in Neuroengineering

Neuroprostheses are neuroengineering devices that have an interface with the nervous system and supplement or substitute functionality in people with disabilities. In the collective imagination, neuroprostheses are mostly used to restore sensory or motor capabilities, but in recent years, new devices directly acting at the brain level have been proposed. In order to design the next-generation of neuroprosthetic devices for brain repair, we foresee the increasing exploitation of closed-loop systems enabled with neuromorphic elements due to their intrinsic energy efficiency, their capability to perform real-time data processing, and of mimicking neurobiological computation for an improved synergy between the technological and biological counterparts. In this manuscript, after providing definitions of key concepts, we reviewed the first exploitation of a real-time hardware neuromorphic prosthesis to restore the bidirectional communication between two neuronal populations in vitro. Starting from that 'case-study', we provide perspectives on the technological improvements for real-time interfacing and processing of neural signals and their potential usage for novel in vitro and in vivo experimental designs. The development of innovative neuroprosthetics for translational purposes is also presented and discussed. In our understanding, the pursuit of neuromorphic-based closed-loop neuroprostheses may spur the development of novel powerful technologies, such as 'brain-prostheses', capable of rewiring and/or substituting the injured nervous system.

A field-programmable gate array (FPGA)-based data acquisition system for closed-loop experiments

We describe a custom and open source field-programmable gate array (FPGA)-based data acquisition (DAQ) system developed for electrophysiology and generally useful for closed-loop feedback experiments. FPGA acquisition and processing are combined with high-speed analog and digital converters to enable real-time feedback. The digital approach eases experimental setup and repeatability by allowing for system identification and in situ tuning of filter bandwidths. The FPGA system includes I2C and serial peripheral interface controllers, 1 GiB dynamic RAM for data buffering, and a USB3 interface to Python software. The DAQ system uses common HDMI connectors to support daughtercards that can be customized for a given experiment to make the system modular and expandable. The FPGA-based digital signal processing (DSP) is used to generate fourth-order digital infinite impulse response filters and feedback with microsecond latency. The FPGA-based DSP and an analog inner-loop are demonstrated via an experiment that rapidly steps the voltage of a capacitor isolated from the system by a considerable resistance using a feedback approach that adjusts the driving voltage based on the digitized capacitor current.

Scalable Thousand Channel Penetrating Microneedle Arrays on Flex for Multimodal and Large Area Coverage BrainMachine Interfaces

The Utah array powers cutting-edge projects for restoration of neurological function, such as BrainGate, but the underlying electrode technology has itself advanced little in the last three decades. Here, advanced dual-side lithographic microfabrication processes is exploited to demonstrate a 1024-channel penetrating silicon microneedle array (SiMNA) that is scalable in its recording capabilities and cortical coverage and is suitable for clinical translation. The SiMNA is the first penetrating microneedle array with a flexible backing that affords compliancy to brain movements. In addition, the SiMNA is optically transparent permitting simultaneous optical and electrophysiological interrogation of neuronal activity. The SiMNA is used to demonstrate reliable recordings of spontaneous and evoked field potentials and of single unit activity in chronically implanted mice for up to 196 days in response to optogenetic and to whisker air-puff stimuli. Significantly, the 1024-channel SiMNA establishes detailed spatiotemporal mapping of broadband brain activity in rats. This novel scalable and biocompatible SiMNA with its multimodal capability and sensitivity to broadband brain activity will accelerate the progress in fundamental neurophysiological investigations and establishes a new milestone for penetrating and large area coverage microelectrode arrays for brain-machine interfaces.

From End to End: Gaining, Sorting, and Employing High-Density Neural Single Unit Recordings

The meaning behind neural single unit activity has constantly been a challenge, so it will persist in the foreseeable future. As one of the most sourced strategies, detecting neural activity in high-resolution neural sensor recordings and then attributing them to their corresponding source neurons correctly, namely the process of spike sorting, has been prevailing so far. Support from ever-improving recording techniques and sophisticated algorithms for extracting worthwhile information and abundance in clustering procedures turned spike sorting into an indispensable tool in electrophysiological analysis. This review attempts to illustrate that in all stages of spike sorting algorithms, the past 5 years innovations' brought about concepts, results, and questions worth sharing with even the non-expert user community. By thoroughly inspecting latest innovations in the field of neural sensors, recording procedures, and various spike sorting strategies, a skeletonization of relevant knowledge lays here, with an initiative to get one step closer to the original objective: deciphering and building in the sense of neural transcript.

Algorithm and hardware considerations for real-time neural signal on-implant processing

Objective Various on-workstation neural-spike-based brain machine interface(BMI) systems have reached the point of in-human trials, but on-node and on-implant BMI systems are still under exploration. Such systems are constrained by the area and battery. Researchers should consider the algorithm complexity, available resources, power budgets, CMOS technologies, and the choice of platforms when designing BMI systems. However, the effect of these factors is currently still unclear. Approaches. Here we have proposed a novel real-time 128 channel spike detection algorithm and optimised it on Microcontroller(MCU) and Field Programmable Gate Array(FPGA) platforms towards consuming minimal power and memory/resources. It is presented as a use case to explore the different considerations in system design. Main results. The proposed spike detection algorithm achieved over 97% sensitivity and a smaller than 3% false detection rate. The MCU implementation occupies less than 3KB RAM and consumes 31.5μW/ch. The FPGA platform only occupies 299 logic cells and 3KB RAM for 128 channels and consumes 0.04μW/ch. Significance. On the spike detection algorithm front, we have eliminated the processing bottleneck by reducing the dynamic power consumption to lower than the hardware static power, without sacrificing detection performance. More importantly, we have explored the considerations in algorithm and hardware design with respect to scalability, portability, and costs. These findings can facilitate and guide the future development of real-time on-implant neural signal processing platforms.

SpikeOnChip : A Custom Embedded Platform for Neuronal Activity Recording and Analysis

In this paper we present SpikeOnChip, a custom embedded platform for neuronal activity recording and online analysis. The SpikeOnChip platform was developed in the context of automated drug testing and toxicology assessments on neural tissue made from human induced pluripotent stem cells. The system was developed with the following goals: to be small, autonomous and low power, to handle micro-electrode arrays with up to 256 electrodes, to reduce the amount of data generated from the recording, to be able to do computation during acquisition, and to be customizable. This led to the choice of a Field Programmable Gate Array System-On-Chip platform. This paper focuses on the embedded system for acquisition and processing with key features being the ability to record electrophysiological signals from multiple electrodes, detect biological activity on all channels online for recording, and do frequency domain spectral energy analysis online on all channels during acquisition. Development methodologies are also presented. The platform is finally illustrated in a concrete experiment with bicuculline being administered to grown human neural tissue through microfluidics, resulting in measurable effects in the spike recordings and activity. The presented platform provides a valuable new experimental instrument that can be further extended thanks to the programmable hardware and software.

An Embedded Multi-Core Real-Time Simulation Platform of Basal Ganglia for Deep Brain Stimulation

Closed-loop deep brain stimulation (DBS) paradigm is gaining tremendous favor due to its potential capability of further and more efficient improvements in neurological diseases. Preclinical validation of closed-loop controller is quite necessary in order to minimize injury risks of clinical trials to patients, which can greatly benefit from real-time computational models and thus potentially reduce research and development costs and time. Here we developed an embedded multi-core real-time simulation platform (EMC-RTP) for a biological-faithful computational network model of basal ganglia (BG). The single neuron model is implemented in a highly real-time manner using a reasonable simplification. A modular mapping architecture with hierarchical routing organization was constructed to mimic the pathological neural activities of BG observed in parkinsonian conditions. A closed-loop simulation testbed for DBS validation was then set up using a host computer as the DBS controller. The availability of EMC-RTP and the testbed system was validated by comparing the performance of open-loop and proportional-integral (PI) controllers. Our experimental results showed that the proposed EMC-RTP reproduces abnormal beta bursts of BG in parkinsonian conditions while meets requirements of both real-time and computational accuracy as well. Closed-loop DBS experiments using the EMC-RTP suggested that the platform could perform reasonable output under different kinds of DBS strategies, indicating the usability of the platform.

Spatial Information Based OSort for Real-Time Spike Sorting Using FPGA

OBJECTIVE

Spiking activity of individual neurons can be separated from the acquired multi-unit activity with spike sorting methods. Processing the recorded high-dimensional neural data can take a large amount of time when performed on general-purpose computers.

METHODS

In this paper, an FPGA-based real-time spike sorting system is presented which takes into account the spatial correlation between the electrical signals recorded with closely-packed recording sites to cluster multi-channel neural data. The system uses a spatial window-based version of the Online Sorting algorithm, which uses unsupervised template-matching for clustering.

RESULTS

The test results show that the proposed system can reach an average accuracy of 86% using simulated data (16-32 neurons, 4-10 dB Signal-to-Noise Ratio), while the single-channel clustering version achieves only 74% average accuracy in the same cases on a 128-channel electrode array. The developed system was also tested on in vivo cortical recordings obtained from an anesthetized rat.

CONCLUSION

The proposed FPGA-based spike sorting system can process more than 11000 spikes/second, so it can be used during in vivo experiments providing real-time feedback on the location and electrophysiological properties of well-separable single units.

SIGNIFICANCE

The proposed spike sorting system could be used to reduce the positioning error of the closely-packed recording site during a neural measurement.

A Real-Time Spike Sorting System Using Parallel OSort Clustering

This article presents an efficient design and implementation of a real-time spike sorting system using unsupervised clustering. We utilize the online sorting (OSort) algorithm and model it first in both floating-point and fixed-point numerical representations to accurately assess the feasibility of our hardware architecture and also reliably analyze the sorting accuracy. For efficient hardware realization of OSort, we propose a modified parallel OSort algorithm. By reducing the number of required memory accesses, the number of computations performed for the management and upkeep of cluster averages and cluster merging is substantially reduced. By limiting the number of supported clusters per channel, the classification/clustering latency is significantly reduced compared to the previously published work, making the designed OSort system applicable for in-vivo spike sorting. The proposed OSort hardware architecture utilizes a novel memory configuration scheme to parallelize the OSort algorithm, which allows us to avoid using relatively large memory queues for storing detected spike waveforms and process them concurrently to the spike cluster management. The characteristics and implementation results of the designed OSort-based spike sorting system on a Xilinx Artix-7 field-programmable gate array (FPGA) are presented. The ASIC implementation of the designed system is estimated to occupy 2.57 mm² in a standard 32-nm CMOS process. Post-layout power estimation shows that the ASIC will dissipate 2.78 mW, while operating at 24 kHz.

Low-latency single channel real-time neural spike sorting system based on template matching

Recent technical advancements in neural engineering allow for precise recording and control of neural circuits simultaneously, opening up new opportunities for closed-loop neural control. In this work, a rapid spike sorting system was developed based on template matching to rapidly calculate instantaneous firing rates for each neuron in a multi-unit extracellular recording setting. Cluster templates were first generated by a desktop computer using a non-parameter spike sorting algorithm (Super-paramagnetic clustering) and then transferred to a field-programmable gate array digital circuit for rapid sorting through template matching. Two different matching techniques–Euclidean distance (ED) and correlational matching (CM)–were compared for the accuracy of sorting and the performance of calculating firing rates. The performance of the system was first verified using publicly available artificial data and was further confirmed with pre-recorded neural spikes from an anesthetized Mongolian gerbil. Real-time recording and sorting from an awake mouse were also conducted to confirm the system performance in a typical behavioral neuroscience experimental setting. Experimental results indicated that high sorting accuracies were achieved for both template-matching methods, but CM can better handle spikes with non-Gaussian spike distributions, making it more robust for in vivo recording. The technique was also compared to several other off-line spike sorting algorithms and the results indicated that the sorting accuracy is comparable but sorting time is significantly shorter than these other techniques. A low sorting latency of under 2 ms and a maximum spike sorting rate of 941 spikes/second have been achieved with our hybrid hardware/software system. The low sorting latency and fast sorting rate allow future system developments of neural circuit modulation through analyzing neural activities in real-time.

Improving an open-source commercial system to reliably perform activity-dependent stimulation

OBJECTIVE

Activity-dependent stimulation (ADS) is designed to strengthen the connections between neuronal circuits and therefore may be a promising tool for promoting neurophysiological reorganization following a brain injury. To successfully perform this technique, two criteria must be met: (1) spikes in the extracellular electrical field potential must be detected accurately at one site of interest, and (2) stimulation pulses generated at fixed (<1 ms jitter), low-latency (<10 ms) intervals relative to each detected spike must be delivered reliably to a second site of interest. Here, we aimed to improve noise rejection in a low-cost commercial system to reliably perform ADS in awake, behaving rats, while maintaining latency requirements.

APPROACH

We implemented a spike detection state machine on a field-programmable gate array (FPGA). Because the accuracy of spike detection can be heavily reduced in awake and behaving animals due to biological artifacts such as movement and chewing, the state machine tracks candidate spike waveforms, checking them against multiple programmable thresholds and rejecting any spikes that fail to meet a programmed threshold criterion.

MAIN RESULTS

A series of offline analyses showed that our implementation was able to appropriately trigger stimulation during epochs of biological artifacts with an overall accuracy between 72% and 97%, fixed computational latency of 167 µs, and an algorithmic latency of 300 µs to 800 µs.

SIGNIFICANCE

Our improvements have been made open-source and are freely available to all scientists working on closed-loop neuroprosthetic devices. Importantly, the improvements are easily incorporated into existing workflows that utilize the Intan Stimulation and Recording Controller.

Computationally efficient fully-automatic online neural spike detection and sorting in presence of multi-unit activity for implantable circuits

BACKGROUND

Spike sorting is a basic step for implantable neural interfaces. With the growing number of channels, the process should be computationally efficient, automatic,robust and applicable on implantable circuits.

NEW METHOD

The proposed method is a combination of fully-automatic offline and online processes. It introduces a novel method for automatically determining a data-aware spike detection threshold, computationally efficient spike feature extraction, automatic optimal cluster number evaluation and verification coupled with Self-Organizing Maps to accurately determine cluster centroids. The system has the ability of unsupervised online operation after initial fully-automatic offline training. The prime focus of this paper is to fully-automate the complete spike detection and sorting pipeline, while keeping the accuracy high.

RESULTS

The proposed system is simulated on two well-known datasets. The automatic threshold improves detection accuracies significantly( > 15%) as compared to the most common detector. The system is able to effectively handle background multi-unit activity with improved performance.

COMPARISON

Most of the existing methods are not fully-automatic; they require supervision and expert intervention at various stages of the pipeline. Secondly, existing works focus on foreground neural activity. Recent research has highlighted importance of background multi-unit activity, and this work is amongst the first efforts that proposes and verifies an automatic methodology to effectively handle them as well.

CONCLUSION

This paper proposes a fully-automatic, computationally efficient system for spike sorting for both single-unit and multi-unit spikes. Although the scope of this work is design and verification through computer simulations, the system has been designed to be easily transferable into an integrated hardware form.

An Efficient Hardware Architecture for Template Matching-Based Spike Sorting

This paper presents an efficient hardware architecture for the design and implementation of a spike sorting system using online template matching. Over the past decade, various spike sorting algorithms have been proposed; however, due to their computational complexity, they may not be suitable for implantable devices that have stringent area and power consumption requirements. We first developed a software-based spike sorting system in both floating-point and fixed-point representations. Then, we used our developed software-based spike sorting system for: 1) studying various neural signal processing algorithms and assessing their feasibility for efficient hardware implementations; and 2) offline processing of previously recorded neural data and extracting the threshold data and spike templates for configuring our spike sorting hardware architecture. The characteristics and implementation results of the designed spike sorting system on a Xilinx Artix-7 A200TFBG676-2 field-programmable gate array are presented. The application-specific integrated circuit (ASIC) implementation of the designed spike sorting system is estimated to occupy 0.3 mm². Postlayout synthesis and simulation shows that the ASIC implementation will dissipate 64 nW from a 0.25-V supply, while operating at a 24-kHz frequency in a standard 45-nm CMOS technology. Compared to the previously published work, our ASIC implementation consumes 96.8% less power, while maintaining a comparable sorting accuracy. Moreover, our design can run at a higher clock frequency and uses fewer hardware resources, while achieving a 168% reduction in output data rate when comparing the raw data sampling rate and the sorted spike output rate and, yet, offers comparable spike sorting accuracy.

Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays

Microelectrode array (MEA) systems with up to several thousands of recording electrodes and electrical or optical stimulation capabilities are commercially available or described in the literature. By exploiting their submillisecond and micrometric temporal and spatial resolutions to record bioelectrical signals, such emerging MEA systems are increasingly used in neuroscience to study the complex dynamics of neuronal networks and brain circuits. However, they typically lack the capability of implementing real-time feedback between the detection of neuronal spiking events and stimulation, thus restricting large-scale neural interfacing to open-loop conditions. In order to exploit the potential of such large-scale recording systems and stimulation, we designed and validated a fully reconfigurable FPGA-based processing system for closed-loop multichannel control. By adopting a Xilinx Zynq-all-programmable system on chip that integrates reconfigurable logic and a dual-core ARM-based processor on the same device, the proposed platform permits low-latency preprocessing (filtering and detection) of spikes acquired simultaneously from several thousands of electrode sites. To demonstrate the proposed platform, we tested its performances through ex vivo experiments on the mice retina using a state-of-the-art planar high-density MEA that samples 4096 electrodes at 18 kHz and record light-evoked spikes from several thousands of retinal ganglion cells simultaneously. Results demonstrate that the platform is able to provide a total latency from whole-array data acquisition to stimulus generation below 2 ms. This opens the opportunity to design closed-loop experiments on neural systems and biomedical applications using emerging generations of planar or implantable large-scale MEA systems.