Ultralow contact resistance between semimetal and monolayer semiconductors

Nonmetallic modified zero-valent iron for remediating halogenated organic compounds and heavy metals: A comprehensive review

Zero Valent Iron (ZVI), an ideal reductant treating persistent pollutants, is hampered by issues like corrosion, passivation, and suboptimal utilization. Recent advancements in nonmetallic modified ZVI (NM-ZVI) show promising potential in circumventing these challenges by modifying ZVI's surface and internal physicochemical properties. Despite its promise, a thorough synthesis of research advancements in this domain remains elusive. Here we review the innovative methodologies, regulatory principles, and reduction-centric mechanisms underpinning NM-ZVI's effectiveness against two prevalent persistent pollutants: halogenated organic compounds and heavy metals. We start by evaluating different nonmetallic modification techniques, such as liquid-phase reduction, mechanical ball milling, and pyrolysis, and their respective advantages. The discussion progresses towards a critical analysis of current strategies and mechanisms used for NM-ZVI to enhance its reactivity, electron selectivity, and electron utilization efficiency. This is achieved by optimizing the elemental compositions, content ratios, lattice constants, hydrophobicity, and conductivity. Furthermore, we propose novel approaches for augmenting NM-ZVI's capability to address complex pollution challenges. This review highlights NM-ZVI's potential as an alternative to remediate water environments contaminated with halogenated organic compounds or heavy metals, contributing to the broader discourse on green remediation technologies.

Identification of the conductivity type of single-walled carbon nanotubes via dual-modulation dielectric force microscopy

The conductivity type is one of the most fundamental transport properties of semiconductors, which is usually identified by fabricating the field-effect transistor, the Hall-effect device, etc. However, it is challenging to obtain an Ohmic contact if the sample is down to nanometer-scale because of the small size and intrinsic heterogeneity. Noncontact dielectric force microscopy (DFM) can identify the conductivity type of the sample by applying a DC gate voltage to the tip, which is effective in tuning the accumulation or depletion of charge carriers. Here, we further developed a dual-modulation DFM, which simplified the conductivity type identification from multiple scan times under different DC gate voltages to a single scan under an AC gate voltage. Taking single-walled carbon nanotubes as testing samples, the semiconducting-type sample exhibits a more significant charge carrier accumulation/depletion under each half-period of the AC gate voltage than the metallic-type sample due to the stronger rectification effect. The charge carrier accumulation or depletion of the p-type sample is opposite to that of the n-type sample at the same half-period of the AC gate voltage because of the reversed charge carrier type.

Computational investigations of the metal/semiconductor NbS2/boron phosphide van der Waals heterostructure: effects of an electric field

In this work, we design computationally the metal-semiconductor NbS2/BP heterostructure and investigate its atomic structure, electronic properties and contact barrier using first-principles prediction. Our results show that the M-S NbS2/BP heterostructure is energetically stable and is characterized by weak vdW interactions. Interestingly, we find that the combination of the metallic NbS2 and semiconducting BP layers leads to the formation of a M-S contact. The M-S NbS2/BP heterostructure exhibits a p-type Schottky contact and a low tunneling-specific resistivity of 3.98 × 10-10 Ω cm2, indicating that the metallic NbS2 can be considered as an efficient 2D electrical contact to the semiconducting BP layer to design NbS2/BP heterostructure-based electronic devices with high charge injection efficiency. The contact barrier and contact type in the M-S NbS2/BP heterostructure can be adjusted by applying an external electric field. The conversion from p-type ShC to n-type ShC can be achieved by applying a negative electric field, while the transformation from ShC to OhC type can be achieved under the application of a positive electric field. The conversion between p-type and n-type ShC and ShC to OhC type in the NbS2/BP heterostructure demonstrates that it can be considered as a promising material for next-generation electronic devices.

Constrained patterning of orientated metal chalcogenide nanowires and their growth mechanism

One-dimensional metallic transition-metal chalcogenide nanowires (TMC-NWs) hold promise for interconnecting devices built on two-dimensional (2D) transition-metal dichalcogenides, but only isotropic growth has so far been demonstrated. Here we show the direct patterning of highly oriented Mo6Te6 NWs in 2D molybdenum ditelluride (MoTe2) using graphite as confined encapsulation layers under external stimuli. The atomic structural transition is studied through in-situ electrical biasing the fabricated heterostructure in a scanning transmission electron microscope. Atomic resolution high-angle annular dark-field STEM images reveal that the conversion of Mo6Te6 NWs from MoTe2 occurs only along specific directions. Combined with first-principles calculations, we attribute the oriented growth to the local Joule-heating induced by electrical bias near the interface of the graphite-MoTe2 heterostructure and the confinement effect generated by graphite. Using the same strategy, we fabricate oriented NWs confined in graphite as lateral contact electrodes in the 2H-MoTe2 FET, achieving a low Schottky barrier of 11.5 meV, and low contact resistance of 43.7 Ω µm at the metal-NW interface. Our work introduces possible approaches to fabricate oriented NWs for interconnections in flexible 2D nanoelectronics through direct metal phase patterning.

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

Controlled Fabrication of Metallic MoO2 Nanosheets towards High-Performance p-Type 2D Transistors

Two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDCs) are extensively employed as channel materials in advanced electronic devices. The electrical contacts between electrodes and 2D semiconductors play a crucial role in the development of high-performance transistors. While numerous strategies for electrode interface engineering have been proposed to enhance the performance of n-type 2D transistors, upgrading p-type ones in a similar manner remains a challenge. In this work, significant improvements in a p-type WSe2 transistor are demonstrated by utilizing metallic MoO2 nanosheets as the electrode contact, which are controllably fabricated through physical vapor deposition and subsequent annealing. The MoO2 nanosheets exhibit an exceptional electrical conductivity of 8.4 × 104 S m‒1 and a breakdown current density of 3.3 × 106 A cm‒2. The work function of MoO2 nanosheets is determined to be ≈5.1 eV, making them suitable for contacting p-type 2D semiconductors. Employing MoO2 nanosheets as the electrode contact in WSe2 transistors results in a notable increase in the field-effect mobility to 92.0 cm2 V‒1 s‒1, which is one order of magnitude higher than the counterpart devices with conventional electrodes. This study not only introduces an intriguing 2D metal oxide to improve the electrical contact in p-type 2D transistors, but also offers an effective approach to fabricating all-2D devices.

Epitaxial Growth of Two-Dimensional MoO2-MoSe2 Metal-Semiconductor Heterostructures for Schottky Diodes

The metal-semiconductor interface fabricated by conventional methods often suffers from contamination, degrading transport performance. Herein, we propose a one-pot chemical vapor deposition (CVD) process to create a two-dimensional (2D) MoO2-MoSe2 heterostructure by growing MoO2 seeds under a hydrogen environment, followed by depositing MoSe2 on the surface and periphery. The ultraclean interface is verified by cross-sectional scanning transmission electron microscopy and photoluminescence. Along with the high work function of semimetallic MoO2 (Ef = -5.6 eV), a high-rectification Schottky diode is fabricated based on this heterostructure. Furthermore, the Schottky diode exhibits an excellent photovoltaic effect with a high open-circuit voltage of 0.26 eV and ultrafast photoresponse, owing to the naturally formed metal-semiconductor contact with suppressed pinning effect. Our method paves the way for the fabrication of an ultraclean 2D metal-semiconductor interface, without defects or contamination, offering promising prospects for future nanoelectronics.

Harnessing Persistent Photocurrent in a 2D Semiconductor-Polymer Hybrid Structure: Electron Trapping and Fermi Level Modulation for Optoelectronic Memory

Recently, 2D semiconductor-based optoelectronic memory has been explored to overcome the limitations of conventional von Neumann architectures by integrating optical sensing and data storage into one device. Persistent photocurrent (PPC), essential for optoelectronic memory, originates from charge carrier trapping according to the Shockley-Read-Hall (SRH) model in 2D semiconductors. The quasi-Fermi level position influences the activation of charge-trapping sites. However, the correlation between quasi-Fermi level modulations and PPC in 2D semiconductors has not been extensively studied. In this study, we demonstrate optoelectronic memory based on a 2D semiconductor-polymer hybrid structure and confirm that the underlying mechanism is charge trapping, as the SRH model explains. Under light illumination, electrons transfer from polyvinylpyrrolidone to p-type tungsten diselenide, resulting in high-level injection and majority carrier-type transitions. The quasi-Fermi level shifts upward with increasing temperature, improving PPC and enabling optoelectronic memory at 433 K. Our findings offer valuable insights into optimizing 2D semiconductor-based optoelectronic memory.

Localized Surface Doping Induced Ultralow Contact Resistance between Metal and (Bi,Sb)2Te3 Thermoelectric Films

Micro thermoelectric devices are expected to further improve the cooling density for the temperature control of electronic devices; nevertheless, the high contact resistivity between metals and semiconductors critically limits their applications, especially in chip cooling with extremely high heat flux. Herein, based on the calculated results, a low specific contact resistivity of ∼10-7 Ω cm2 at the interface is required to guarantee a desirable cooling power density of micro devices. Thus, we developed a generally applicable interfacial modulation strategy via localized surface doping of thermoelectric films, and the feasibility of such a doping approach for both n/p-type (Bi,Sb)2Te3 films was demonstrated, which can effectively increase the surface-majority carrier concentration explained by the charge transfer mechanism. With a proper doping level, ultralow specific contact resistivities at the interfaces are obtained for n-type (6.71 × 10-8 Ω cm2) and p-type (3.70 × 10-7 Ω cm2) (Bi,Sb)2Te3 layers, respectively, which is mainly attributed to the carrier tunneling enhancement with a narrowed interfacial contact barrier width. This work provides an effective scheme to further reduce the internal resistance of micro thermoelectric coolers, which can also be extended as a kind of universal interfacial modification technique for micro semiconductor devices.

Boosting Monolayer Transition Metal Dichalcogenides Growth by Hydrogen-Free Ramping during Chemical Vapor Deposition

The controlled vapor-phase synthesis of two-dimensional (2D) transition metal dichalcogenides (TMDs) is essential for functional applications. While chemical vapor deposition (CVD) techniques have been successful for transition metal sulfides, extending these methods to selenides and tellurides often faces challenges due to uncertain roles of hydrogen (H2) in their synthesis. Using CVD growth of MoSe2 as an example, this study illustrates the role of a H2-free environment during temperature ramping in suppressing the reduction of MoO3, which promotes effective vaporization and selenization of the Mo precursor to form MoSe2 monolayers with excellent crystal quality. As-synthesized MoSe2 monolayer-based field-effect transistors show excellent carrier mobility of up to 20.9 cm2/(V·s) with an on-off ratio of 7 × 107. This approach can be extended to other TMDs, such as WSe2, MoTe2, and MoSe2/WSe2 in-plane heterostructures. Our work provides a rational and facile approach to reproducibly synthesize high-quality TMD monolayers, facilitating their translation from laboratory to manufacturing.

Antimony-Platinum Modulated Contact Enabling Majority Carrier Polarity Selection on a Monolayer Tungsten Diselenide Channel

We develop a novel metal contact approach using an antimony (Sb)-platinum (Pt) bilayer to mitigate Fermi-level pinning in 2D transition metal dichalcogenide channels. This strategy allows for control over the transport polarity in monolayer WSe2 devices. By adjustment of the Sb interfacial layer thickness from 10 to 30 nm, the effective work function of the contact/WSe2 interface can be tuned from 4.42 eV (p-type) to 4.19 eV (n-type), enabling selectable n-/p-FET operation in enhancement mode. The shift in effective work function is linked to Sb-Se bond formation and an emerging n-doping effect. This work demonstrates high-performance n- and p-FETs with a single WSe2 channel through Sb-Pt contact modulation. After oxide encapsulation, the maximum current density at |VD| = 1 V reaches 170 μA/μm for p-FET and 165 μA/μm for n-FET. This approach shows promise for cost-effective CMOS transistor applications using a single channel material and metal contact scheme.

Innovations of metallic contacts on semiconducting 2D transition metal dichalcogenides toward advanced 3D-structured field-effect transistors

2D semiconductors, represented by transition metal dichalcogenides (TMDs), have the potential to be alternative channel materials for advanced 3D field-effect transistors, such as gate-all-around field-effect-transistors (GAAFETs) and complementary field-effect-transistors (C-FETs), due to their inherent atomic thinness, moderate mobility, and short scaling lengths. However, 2D semiconductors encounter several technological challenges, especially the high contact resistance issue between 2D semiconductors and metals. This review provides a comprehensive overview of the high contact resistance issue in 2D semiconductors, including its physical background and the efforts to address it, with respect to their applicability to GAAFET structures.

Interfacial epitaxy of multilayer rhombohedral transition-metal dichalcogenide single crystals

Rhombohedral-stacked transition-metal dichalcogenides (3R-TMDs), which are distinct from their hexagonal counterparts, exhibit higher carrier mobility, sliding ferroelectricity, and coherently enhanced nonlinear optical responses. However, surface epitaxial growth of large multilayer 3R-TMD single crystals is difficult. We report an interfacial epitaxy methodology for their growth of several compositions, including molybdenum disulfide (MoS2), molybdenum diselenide, tungsten disulfide, tungsten diselenide, niobium disulfide, niobium diselenide, and molybdenum sulfoselenide. Feeding of metals and chalcogens continuously to the interface between a single-crystal Ni substrate and grown layers ensured consistent 3R stacking sequence and controlled thickness from a few to 15,000 layers. Comprehensive characterizations confirmed the large-scale uniformity, high crystallinity, and phase purity of these films. The as-grown 3R-MoS2 exhibited room-temperature mobilities up to 155 and 190 square centimeters per volt second for bi- and trilayers, respectively. Optical difference frequency generation with thick 3R-MoS2 showed markedly enhanced nonlinear response under a quasi-phase matching condition (five orders of magnitude greater than monolayers).

Integrated 1D epitaxial mirror twin boundaries for ultrascaled 2D MoS2 field-effect transistors

In atomically thin van der Waals materials, grain boundaries-the line defects between adjacent crystal grains with tilted in-plane rotations-are omnipresent. When the tilting angles are arbitrary, the grain boundaries form inhomogeneous sublattices, giving rise to local electronic states that are not controlled. Here we report on epitaxial realizations of deterministic MoS2 mirror twin boundaries (MTBs) at which two adjoining crystals are reflection mirroring by an exactly 60° rotation by position-controlled epitaxy. We showed that these epitaxial MTBs are one-dimensionally metallic to a circuit length scale. By utilizing the ultimate one-dimensional (1D) feature (width ~0.4 nm and length up to a few tens of micrometres), we incorporated the epitaxial MTBs as a 1D gate to build integrated two-dimensional field-effect transistors (FETs). The critical role of the 1D MTB gate was verified to scale the depletion channel length down to 3.9 nm, resulting in a substantially lowered channel off-current at lower gate voltages. With that, in both individual and array FETs, we demonstrated state-of-the-art performances for low-power logics. The 1D epitaxial MTB gates in this work suggest a novel synthetic pathway for the integration of two-dimensional FETs-that are immune to high gate capacitance-towards ultimate scaling.

Flexoelectricity Modulated Electron Transport of 2D Indium Oxide

The phenomenon of flexoelectricity, wherein mechanical deformation induces alterations in the electron configuration of metal oxides, has emerged as a promising avenue for regulating electron transport. Leveraging this mechanism, stress sensing can be optimized through precise modulation of electron transport. In this study, the electron transport in 2D ultra-smooth In2O3 crystals is modulated via flexoelectricity. By subjecting cubic In2O3 (c-In2O3) crystals to significant strain gradients using an atomic force microscope (AFM) tip, the crystal symmetry is broken, resulting in the separation of positive and negative charge centers. Upon applying nano-scale stress up to 100 nN, the output voltage and power values reach their maximum, e.g. 2.2 mV and 0.2 pW, respectively. The flexoelectric coefficient and flexocoupling coefficient of c-In2O3 are determined as ≈0.49 nC m-1 and 0.4 V, respectively. More importantly, the sensitivity of the nano-stress sensor upon c-In2O3 flexoelectric effect reaches 20 nN, which is four to six orders smaller than that fabricated with other low dimensional materials based on the piezoresistive, capacitive, and piezoelectric effect. Such a deformation-induced polarization modulates the band structure of c-In2O3, significantly reducing the Schottky barrier height (SBH), thereby regulating its electron transport. This finding highlights the potential of flexoelectricity in enabling high-performance nano-stress sensing through precise control of electron transport.

In situ via Contact to hBN-Encapsulated Air-Sensitive Atomically Thin Semiconductors

Establishing reliable electrical contacts to atomically thin materials is a prerequisite for both fundamental studies and applications yet remains a challenge. In particular, the development of contact techniques for air-sensitive monolayers has lagged behind, despite their unique properties and significant potential for applications. Here, we present a robust method to create contacts to device layers encapsulated within hexagonal boron nitride (hBN). This method uses plasma etching and metal deposition to create 'vias' in the hBN with graphene forming an atomically thin etch-stop. The resulting partially fluorinated graphene (PFG) protects the underlying device layer from air-induced degradation and damage during metal deposition. PFG is resistive in-plane but maintains high out-of-plane conductivity. The work function of the PFG/metal contact is tunable through the degree of fluorination, offering opportunities for contact engineering. Using the in situ via technique, we achieve ambipolar contact to air-sensitive monolayer 2H-molybdenum ditelluride (MoTe2) with more than 1 order of magnitude improvement in on-current density compared to previous literature. The complete encapsulation provides high reproducibility and long-term stability. The technique can be extended to other air-sensitive materials as well as air-stable materials, offering highly competitive device performance.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5 V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60 mV dec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

The future of two-dimensional semiconductors beyond Moore's law

The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration.

The Contact Properties of Monolayer and Multilayer MoS2-Metal van der Waals Interfaces

The contact resistance formed between MoS2 and metal electrodes plays a key role in MoS2-based electronic devices. The Schottky barrier height (SBH) is a crucial parameter for determining the contact resistance. However, the SBH is difficult to modulate because of the strong Fermi-level pinning (FLP) at MoS2-metal interfaces. Here, we investigate the FLP effect and the contact types of monolayer and multilayer MoS2-metal van der Waals (vdW) interfaces using density functional theory (DFT) calculations based on Perdew-Burke-Ernzerhof (PBE) level. It has been demonstrated that, compared with monolayer MoS2-metal close interfaces, the FLP effect can be significantly reduced in monolayer MoS2-metal vdW interfaces. Furthermore, as the layer number of MoS2 increases from 1L to 4L, the FLP effect is first weakened and then increased, which can be attributed to the charge redistribution at the MoS2-metal and MoS2-MoS2 interfaces. In addition, the p-type Schottky contact can be achieved in 1L-4L MoS2-Pt, 3L MoS2-Au, and 2L-3L MoS2-Pd vdW interfaces, which is useful for realizing complementary metal oxide semiconductor (CMOS) logic circuits. These findings indicated that the FLP and contact types can be effectively modulated at MoS2-metal vdW interfaces by selecting the layer number of MoS2.

Projected performance of Si- and 2D-material-based SRAM circuits ranging from 16 nm to 1 nm technology nodes

Researchers have been developing 2D materials (2DM) for electronics, which are widely considered a possible replacement for silicon in future technology. Two-dimensional transition metal dichalcogenides are the most promising among the different materials due to their electronic performance and relatively advanced development. Although field-effect transistors (FETs) based on 2D transition metal dichalcogenides have been found to outperform Si in ultrascaled devices, the comparison of 2DM-based and Si-based technologies at the circuit level is still missing. Here we compare 2DM- and Si FET-based static random-access memory (SRAM) circuits across various technology nodes from 16 nm to 1 nm and reveal that the 2DM-based SRAM exhibits superior performance in terms of stability, operating speed and energy efficiency when compared with Si SRAM. This study utilized technology computer-aided design to conduct device and circuit simulations, employing calibrated MoS2 nFETs and WSe2 pFETs. It incorporated layout design rules across various technology nodes to comprehensively analyse their SRAM functionality. The results show that, compared with three-dimensional structure Si transistors at 1 nm node, the planar 2DMFETs exhibited lower capacitance, leading to reduced cell read access time (-16%), reduced time to write (-72%) and lowered dynamic power (-60%). The study highlights the provisional benefits of using planar 2DM transistors to mitigate the performance degradation caused by reduced metal pitch and increased wire resistance in advanced nodes, potentially opening up exciting possibilities for high-performance and low-power circuit applications.

Enhancing 2D Photonics and Optoelectronics with Artificial Microstructures

By modulating subwavelength structures and integrating functional materials, 2D artificial microstructures (2D AMs), including heterostructures, superlattices, metasurfaces and microcavities, offer a powerful platform for significant manipulation of light fields and functions. These structures hold great promise in high-performance and highly integrated optoelectronic devices. However, a comprehensive summary of 2D AMs remains elusive for photonics and optoelectronics. This review focuses on the latest breakthroughs in 2D AM devices, categorized into electronic devices, photonic devices, and optoelectronic devices. The control of electronic and optical properties through tuning twisted angles is discussed. Some typical strategies that enhance light-matter interactions are introduced, covering the integration of 2D materials with external photonic structures and intrinsic polaritonic resonances. Additionally, the influences of external stimuli, such as vertical electric fields, enhanced optical fields and plasmonic confinements, on optoelectronic properties is analysed. The integrations of these devices are also thoroughly addressed. Challenges and future perspectives are summarized to stimulate research and development of 2D AMs for future photonics and optoelectronics.

Designing barrier-free metal/MoS2 contacts through electrene insertion

Transition-metal dichalcogenides (TMDCs), including MoS2, have great potential in electronics applications. However, achieving low-resistance metal contacts is a challenge that impacts their performance in nanodevices due to strong Fermi-level pinning and the presence of a tunnelling barrier. As a solution, we explore a strategy of inserting monolayers of alkaline-earth sub-pnictide electrenes with a general formula of [M2X]+e- (M = Ca, Sr, Ba; X = N, P, As, Sb) between the TMDC and the metal. These electrenes possess two-dimensional sheets of charge on their surfaces that can be readily donated when interfaced with a TMDC semiconductor, thereby lowering its conduction band below the Fermi level and eliminating the Schottky and tunnelling barriers. In this work, density-functional theory (DFT) calculations were performed for metal/electrene/MoS2 heterojunctions for all stable M2X electrenes and both Au and Cu metals. To identify the material combinations that provide the most effective Ohmic contact, the charge transfer, band structure, and electrostatic potential were computed. Linear correlations were found between the charge donated to the MoS2 and both the electrene surface charge and work function. Overall, Ca2N appears to be the most promising electrene for achieving an Ohmic metal/MoS2 contact due to its high surface charge density.

Inner Doping of Carbon Nanotubes with Perovskites for Ultralow Power Transistors

Semiconducting carbon nanotubes (CNTs) are considered as the most promising channel material to construct ultrascaled field-effect transistors, but the perfect sp2 C─C structure makes stable doping difficult, which limits the electrical designability of CNT devices. Here, an inner doping method is developed by filling CNTs with 1D halide perovskites to form a coaxial heterojunction, which enables a stable n-type field-effect transistor for constructing complementary metal-oxide-semiconductor electronics. Most importantly, a quasi-broken-gap (BG) heterojunction tunnel field-effect transistor (TFET) is first demonstrated based on an individual partial-filling CsPbBr3/CNT and exhibits a subthreshold swing of 35 mV dec-1 with a high on-state current of up to 4.9 µA per tube and an on/off current ratio of up to 105 at room temperature. The quasi-BG TFET based on the CsPbBr3/CNT coaxial heterojunction paves the way for constructing high-performance and ultralow power consumption integrated circuits.

All van der Waals Semiconducting PtSe2 Field Effect Transistors with Low Contact Resistance Graphite Electrodes

Contact resistance is a multifaceted challenge faced by the 2D materials community. Large Schottky barrier heights and gap-state pinning are active obstacles that require an integrated approach to achieve the development of high-performance electronic devices based on 2D materials. In this work, we present semiconducting PtSe2 field effect transistors with all-van-der-Waals electrode and dielectric interfaces. We use graphite contacts, which enable high ION/IOFF ratios up to 109 with currents above 100 μA μm-1 and mobilities of 50 cm2 V-1 s-1 at room temperature and over 400 cm2 V-1 s-1 at 10 K. The devices exhibit high stability with a maximum hysteresis width below 36 mV nm-1. The contact resistance at the graphite-PtSe2 interface is found to be below 700 Ω μm. Our results present PtSe2 as a promising candidate for the realization of high-performance 2D circuits built solely with 2D materials.

Hydrogen-Bonding Integrated Low-Dimensional Flexible Electronics Beyond the Limitations of van der Waals Contacts

Van der Waals (vdW) integration enables clean contacts for low-dimensional electronic devices. The limitation remains; however, that an additional tunneling contact resistance occurs owing to the inherent vdW gap between the metal and the semiconductor. Here, it is demonstrated from theoretical calculations that stronger non-covalent hydrogen-bonding interactions facilitate electron tunneling and significantly reduce the contact resistance; thus, promising to break the limitations of the vdW contact. π-plane hydrogen-bonding contacts in surface-engineered MXene/carbon nanotube metal/semiconductor heterojunctions are realized, and an anomalous temperature-dependent tunneling resistance is observed. Low-dimensional flexible thin-film transistors integrated by hydrogen-bonding contacts exhibit both excellent flexibility and carrier mobility orders of magnitude higher than their counterparts with vdW contacts. This strategy demonstrates a scalable solution for realizing high-performance and low-power flexible electronics beyond vdW contacts.

Optimizing Ultrathin 2D Transistors for Monolithic 3D Integration: A Study on Directly Grown Nanocrystalline Interconnects and Buried Contacts

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40 nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7 nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).

Van der Waals polarity-engineered 3D integration of 2D complementary logic

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1-3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6-8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9-17) and MoS2 (refs. 11,18-28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V-1 s-1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

High-κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low-Power Steep-Switching Computing Devices

Herein, a high-quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm-2 eV-1). The chemically converted HfO2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10-3 A cm-2) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high-quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe2 layer without a substitution energy barrier, allowing layer-by-layer oxidation to proceed. The field-effect-transistor-fabricated HfO2/HfSe2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec-1 (over four orders of IDS) at room temperature (300 K), along with a high Ion/Ioff ratio of ≈108 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO2/HfSe2 gate stack and channel structures, an impact ionization field-effect transistor is fabricated that exhibits n-type steep-switching characteristics with a SS value of 3.43 mV dec-1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post-Si semiconducting devices for future energy-efficient data-centric computing electronics.

Uniform Synthesis of Bilayer Hydrogen Substituted Graphdiyne for Flexible Piezoresistive Applications

Graphdiyne (GDY) has garnered significant attention as a cutting-edge 2D material owing to its distinctive electronic, optoelectronic, and mechanical properties, including high mobility, direct bandgap, and remarkable flexibility. One of the key challenges hindering the implementation of this material in flexible applications is its large area and uniform synthesis. The facile growth of centimeter-scale bilayer hydrogen substituted graphdiyne (Bi-HsGDY) on germanium (Ge) substrate is achieved using a low-temperature chemical vapor deposition (CVD) method. This material's field effect transistors (FET) showcase a high carrier mobility of 52.6 cm2 V-1 s-1 and an exceptionally low contact resistance of 10 Ω µm. By transferring the as-grown Bi-HsGDY onto a flexible substrate, a long-distance piezoresistive strain sensor is demonstrated, which exhibits a remarkable gauge factor of 43.34 with a fast response time of ≈275 ms. As a proof of concept, communication by means of Morse code is implemented using a Bi-HsGDY strain sensor. It is believed that these results are anticipated to open new horizons in realizing Bi-HsGDY for innovative flexible device applications.

Machine Learning to Promote Efficient Screening of Low-Contact Electrode for 2D Semiconductor Transistor Under Limited Data

Low-barrier and high-injection electrodes are crucial for high-performance (HP) 2D semiconductor devices. Conventional trial-and-error methodologies for electrode material screening are impractical because of their low efficiency and arbitrary specificity. Although machine learning has emerged as a promising alternative to tackle this problem, its practical application in semiconductor devices is hindered by its substantial data requirements. In this paper, a comprehensive scheme combining an autoencoding regularized adversarial neural network and a feature-adaptive variational active learning algorithm for screening low-contact electrode materials for 2D semiconductor transistors with limited data is proposed. The proposed scheme exhibits exceptional performance by training with only 15% of the total data points, where the mean square errors are 0.17 and 0.27 eV for the vertical and lateral Schottky barrier, respectively, and 2.88% for tunneling probability. Further, it exhibits an optimal predictive performance for 100 randomly sampled training datasets, reveals the underlying physical insight based on the identified features, and realizes continual improvement by employing detailed density-of-states descriptors. Finally, the empirical evaluations of the transport characteristics are conducted and verified by constructing MOSFET devices. These findings demonstrate the considerable potential of machine-learning techniques for screening high-efficiency electrode materials and constructing HP 2D semiconductor devices.

Identifying atomically thin isolated-band channels for intrinsic steep-slope transistors by high-throughput study

Developing low-power FETs holds significant importance in advancing logic circuits, especially as the feature size of MOSFETs approaches sub-10 nanometers. However, this has been restricted by the thermionic limitation of SS, which is limited to 60 mV per decade at room temperature. Herein, we proposed a strategy that utilizes 2D semiconductors with an isolated-band feature as channels to realize sub-thermionic SS in MOSFETs. Through high-throughput calculations, we established a guiding principle that combines the atomic structure and orbital interaction to identify their sub-thermionic transport potential. This guides us to screen 192 candidates from the 2D material database comprising 1608 systems. Additionally, the physical relationship between the sub-thermionic transport performances and electronic structures is further revealed, which enables us to predict 15 systems with promising device performances for low-power applications with supply voltage below 0.5 V. This work opens a new way for the low-power electronics based on 2D materials and would inspire extensive interests in the experimental exploration of intrinsic steep-slope MOSFETs.

Reliable wafer-scale integration of two-dimensional materials and metal electrodes with van der Waals contacts

Since the first report on single-layer MoS2 based transistor, rapid progress has been achieved in two-dimensional (2D) material-based atomically thin electronics, providing an alternative approach to solve the bottleneck in silicon device miniaturization. In this scenario, reliable contact between the metal electrodes and the subnanometer-thick 2D materials becomes crucial in determining the device performance. Here, utilizing the quasi-van der Waals (vdW) epitaxy of metals on fluorophlogopite mica, we demonstrate an all-stacking method for the fabrication of 2D devices with high-quality vdW contacts by mechanically transferring pre-deposited metal electrodes. This technique is applicable for complex device integration with sizes up to the wafer scale and is also capable of tuning the electric characteristics of the interfacial junctions by transferring selective metals. Our results provide an efficient, scalable, and low-cost technique for 2D electronics, allowing high-density device integration as well as a handy tool for fundamental research in vdW materials.

Oxide and 2D TMD semiconductors for 3D DRAM cell transistors

As the downscaling of conventional dynamic random-access memory (DRAM) has reached its limits, 3D DRAM has been proposed as a next-generation DRAM cell architecture. However, incorporating silicon into 3D DRAM technology faces various challenges in securing cost-effective high cell transistor performance. Therefore, many researchers are exploring the application of next-generation semiconductor materials, such as transition oxide semiconductors (OSs) and metal dichalcogenides (TMDs), to address these challenges and to realize 3D DRAM. This study provides an overview of the proposed structures for 3D DRAM, compares the characteristics of OSs and TMDs, and discusses the feasibility of employing the OSs and TMDs as the channel material for 3D DRAM. Furthermore, we review recent progress in 3D DRAM using the OSs, discussing their potential to overcome challenges in silicon-based approaches.

Trifluoromethylation of 2D Transition Metal Dichalcogenides: A Mild Functionalization and Tunable p-Type Doping Method

Chemical modification is a powerful strategy for tuning the electronic properties of 2D semiconductors. Here we report the electrophilic trifluoromethylation of 2D WSe2 and MoS2 under mild conditions using the reagent trifluoromethyl thianthrenium triflate (TTT). Chemical characterization and density functional theory calculations reveal that the trifluoromethyl groups bind covalently to surface chalcogen atoms as well as oxygen substitution sites. Trifluoromethylation induces p-type doping in the underlying 2D material, enabling the modulation of charge transport and optical emission properties in WSe2. This work introduces a versatile and efficient method for tailoring the optical and electronic properties of 2D transition metal dichalcogenides.

Low Resistance Contact to P-Type Monolayer WSe2

Advanced microelectronics in the future may require semiconducting channel materials beyond silicon. Two-dimensional (2D) semiconductors, with their atomically thin thickness, hold great promise for future electronic devices. One challenge to achieving high-performance 2D semiconductor field effect transistors (FET) is the high contact resistance at the metal-semiconductor interface. In this study, we develop a charge-transfer doping strategy with WSe2/α-RuCl3 heterostructures to achieve low-resistance ohmic contact for p-type monolayer WSe2 transistors. We show that hole doping as high as 3 × 1013 cm-2 can be achieved in the WSe2/α-RuCl3 heterostructure due to its type-III band alignment, resulting in an ohmic contact with resistance of 4 kΩ μm. Based on that, we demonstrate p-type WSe2 transistors with an on-current of 35 μA·μm-1 and an ION/IOFF ratio exceeding 109 at room temperature.

Direct Selective Epitaxy of 2D Sb2Te3 onto Monolayer WS2 for Vertical p-n Heterojunction Photodetectors

Two-dimensional transition metal dichalcogenides (2D-TMDs) possess appropriate bandgaps and interact via van der Waals (vdW) forces between layers, effectively overcoming lattice compatibility challenges inherent in traditional heterojunctions. This property facilitates the creation of heterojunctions with customizable bandgap alignments. However, the prevailing method for creating heterojunctions with 2D-TMDs relies on the low-efficiency technique of mechanical exfoliation. Sb2Te3, recognized as a notable p-type semiconductor, emerges as a versatile component for constructing diverse vertical p-n heterostructures with 2D-TMDs. This study presents the successful large-scale deposition of 2D Sb2Te3 onto inert mica substrates, providing valuable insights into the integration of Sb2Te3 with 2D-TMDs to form heterostructures. Building upon this initial advancement, a precise epitaxial growth method for Sb2Te3 on pre-existing WS2 surfaces on SiO2/Si substrates is achieved through a two-step chemical vapor deposition process, resulting in the formation of Sb2Te3/WS2 heterojunctions. Finally, the development of 2D Sb2Te3/WS2 optoelectronic devices is accomplished, showing rapid response times, with a rise/decay time of 305 μs/503 μs, respectively.

Growth of Quasi-Two-Dimensional CrTe Nanoflakes and CrTe/Transition Metal Dichalcogenide Heterostructures

Two-dimensional (2D) van der Waals layered materials have been explored in depth. They can be vertically stacked into a 2D heterostructure and represent a fundamental way to explore new physical properties and fabricate high-performance nanodevices. However, the controllable and scaled growth of non-layered quasi-2D materials and their heterostructures is still a great challenge. Here, we report a selective two-step growth method for high-quality single crystalline CrTe/WSe2 and CrTe/MoS2 heterostructures by adopting a universal CVD strategy with the assistance of molten salt and mass control. Quasi-2D metallic CrTe was grown on pre-deposited 2D transition metal dichalcogenides (TMDC) under relatively low temperatures. A 2D CrTe/TMDC heterostructure was established to explore the interface's structure using scanning transmission electron microscopy (STEM), and also demonstrate ferromagnetism in a metal-semiconductor CrTe/TMDC heterostructure.

Adjustment methods of Schottky barrier height in one- and two-dimensional semiconductor devices

The Schottky contact which is a crucial interface between semiconductors and metals is becoming increasingly significant in nano-semiconductor devices. A Schottky barrier, also known as the energy barrier, controls the depletion width and carrier transport across the metal-semiconductor interface. Controlling or adjusting Schottky barrier height (SBH) has always been a vital issue in the successful operation of any semiconductor device. This review provides a comprehensive overview of the static and dynamic adjustment methods of SBH, with a particular focus on the recent advancements in nano-semiconductor devices. These methods encompass the work function of the metals, interface gap states, surface modification, image-lowering effect, external electric field, light illumination, and piezotronic effect. We also discuss strategies to overcome the Fermi-level pinning effect caused by interface gap states, including van der Waals contact and 1D edge metal contact. Finally, this review concludes with future perspectives in this field.

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide-semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS2 field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint.

Specific contact resistivity reduction in amorphous IGZO thin-film transistors through a TiN/IGTO heterogeneous interlayer

Oxide semiconductors have gained significant attention in electronic device industry due to their high potential for emerging thin-film transistor (TFT) applications. However, electrical contact properties such as specific contact resistivity (ρC) and width-normalized contact resistance (RCW) are significantly inferior in oxide TFTs compared to conventional silicon metal oxide semiconductor field-effect transistors. In this study, a multi-stack interlayer (IL) consisting of titanium nitride (TiN) and indium-gallium-tin-oxide (IGTO) is inserted between source/drain electrodes and amorphous indium-gallium-zinc-oxide (IGZO). The TiN is introduced to increase conductivity of the underlying layer, while IGTO acts as an n+-layer. Our findings reveal IGTO thickness (tIGTO)-dependent electrical contact properties of IGZO TFT, where ρC and RCW decrease as tIGTO increases to 8 nm. However, at tIGTO > 8 nm, they increase mainly due to IGTO crystallization-induced contact interface aggravation. Consequently, the IGZO TFTs with a TiN/IGTO (3/8 nm) IL reveal the lowest ρC and RCW of 9.0 × 10-6 Ω·cm2 and 0.7 Ω·cm, significantly lower than 8.0 × 10-4 Ω·cm2 and 6.9 Ω·cm in the TFTs without the IL, respectively. This improved electrical contact properties increases field-effect mobility from 39.9 to 45.0 cm2/Vs. This study demonstrates the effectiveness of this multi-stack IL approach in oxide TFTs.

Growth of Single Crystalline 2D Materials beyond Graphene on Non-metallic Substrates

The advent of 2D materials has ushered in the exploration of their synthesis, characterization and application. While plenty of 2D materials have been synthesized on various metallic substrates, interfacial interaction significantly affects their intrinsic electronic properties. Additionally, the complex transfer process presents further challenges. In this context, experimental efforts are devoted to the direct growth on technologically important semiconductor/insulator substrates. This review aims to uncover the effects of substrate on the growth of 2D materials. The focus is on non-metallic substrate used for epitaxial growth and how this highlights the necessity for phase engineering and advanced characterization at atomic scale. Special attention is paid to monoelemental 2D structures with topological properties. The conclusion is drawn through a discussion of the requirements for integrating 2D materials with current semiconductor-based technology and the unique properties of heterostructures based on 2D materials. Overall, this review describes how 2D materials can be fabricated directly on non-metallic substrates and the exploration of growth mechanism at atomic scale.

Semimetallic Bismuthene with Edge-Rich Dangling Bonds: Broad-Spectrum-Driven and Edge-Confined Electron Enhancement Boosting CO2 Hydrogenation Reduction

Broad-spectrum-driven high-performance artificial photosynthesis is quite challenging. Herein, atomically ultrathin bismuthene with semimetallic properties is designed and demonstrated for broad-spectrum (ultraviolet-visible-near infrared light) (UV-vis-NIR)-driven photocatalytic CO2 hydrogenation. The trap states in the bandgap produced by edge dangling bonds prolong the lifetime of the photogenerated electrons from 90 ps in bulk Bi to 1650 ps in bismuthine, and excited-state electrons are enriched at the edge of bismuthine. The edge dangling bonds of bismuthene as the active sites for adsorption/activation of CO2 increase the hybridization ability of the Bi 6p orbital and O 2p orbital to significantly reduce the catalytic reaction energy barrier and promote the formation of C─H bonds until the generation of CH4. Under λ ≥ 400 nm and λ ≥ 550 nm irradiation, the utilization ratios of photogenerated electron reduction CO2 hydrogenation to CO and CH4 for bismuthene are 58.24 and 300.50 times higher than those of bulk Bi, respectively. Moreover, bismuthene can extend the CO2 hydrogenation reaction to the near-infrared region (λ ≥ 700 nm). This pioneering work employs the single semimetal element as an artificial photosynthetic catalyst to produce a broad spectral response.

Can 2D Semiconductors Be Game-Changers for Nanoelectronics and Photonics?

2D semiconductors have interesting physical and chemical attributes that have led them to become one of the most intensely investigated semiconductor families in recent history. They may play a crucial role in the next technological revolution in electronics as well as optoelectronics or photonics. In this Perspective, we explore the fundamental principles and significant advancements in electronic and photonic devices comprising 2D semiconductors. We focus on strategies aimed at enhancing the performance of conventional devices and exploiting important properties of 2D semiconductors that allow fundamentally interesting device functionalities for future applications. Approaches for the realization of emerging logic transistors and memory devices as well as photovoltaics, photodetectors, electro-optical modulators, and nonlinear optics based on 2D semiconductors are discussed. We also provide a forward-looking perspective on critical remaining challenges and opportunities for basic science and technology level applications of 2D semiconductors.

Lowering the Schottky Barrier Height by Quasi-van der Waals Contacts for High-Performance p-Type MoTe2 Field-Effect Transistors

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) offer advantages over traditional silicon in future electronics but are hampered by the prominent high contact resistance of metal-TMD interfaces, especially for p-type TMDs. Here, we present high-performance p-type MoTe2 field-effect transistors via a nondestructive van der Waals (vdW) transfer process, establishing low contact resistance between the 2D MoTe2 semiconductor and the PtTe2 semimetal. The integration of PtTe2 as contacts in MoTe2 field-effect transistors leads to significantly improved electrical characteristics compared to conventional metal contacts, evidenced by a mobility increase to 80 cm2 V-1 s-1, an on-state current rise to 5.0 μA/μm, and a reduction in Schottky barrier height (SBH) to 48 meV. Such a low SBH in quasi-van der Waals contacts can be assigned to the low electrical resistivity of PtTe2 and the high efficiency of carrier injection at the 2D semimetal/2D semiconductor interfaces. Imaging via transmission electron microscopy reveals that the 2D semimetal/two-dimensional semiconductor interfaces are atomically flat and exceptionally clean. This interface engineering strategy could enable low-resistance contacts based on vdW architectures in a facile manner, providing opportunities for 2D materials for next-generation optoelectronics and electronics.

Enhanced Electrical Transport Properties of Molybdenum Disulfide Field-Effect Transistors by Using Alkali Metal Fluorides as Dielectric Capping Layers

The electronic properties of 2D materials are highly influenced by the molecular activity at their interfaces. A method was proposed to address this issue by employing passivation techniques using monolayer MoS2 field-effect transistors (FETs) while preserving high performance. Herein, we have used alkali metal fluorides as dielectric capping layers, including lithium fluoride (LiF), sodium fluoride (NaF), and potassium fluoride (KF) dielectric capping layers, to mitigate the environmental impact of oxygen and water exposure. Among them, the LiF dielectric capping layer significantly improved the transistor performance, specifically in terms of enhanced field effect mobility from 74 to 137 cm2/V·s, increased current density from 17 μA/μm to 32.13 μA/μm at a drain voltage of Vd of 1 V, and decreased subthreshold swing to 0.8 V/dec The results have been analytically verified by X-ray photoelectron spectroscopy (XPS) and Raman, and photoluminescence (PL) spectroscopy, and the demonstrated technique can be extended to other transition metal dichalcogenide (TMD)-based FETs, which can become a prospect for cutting-edge electronic applications. These findings highlight certain important trade-offs and provide insight into the significance of interface control and passivation material choice on the electrical stability, performance, and enhancement of the MoS2 FET.

Direct Assessment of Defective Regions in Monolayer MoS2 Field-Effect Transistors through In Situ Scanning Probe Microscopy Measurements

Implementing two-dimensional materials in field-effect transistors (FETs) offers the opportunity to continue the scaling trend in the complementary metal-oxide-semiconductor technology roadmap. Presently, the search for electrically active defects, in terms of both their density of energy states and their spatial distribution, has turned out to be of paramount importance in synthetic transition metal dichalcogenides layers, as they are suspected of severely inhibiting these devices from achieving their highest performance. Although advanced microscopy tools have allowed the direct detection of physical defects such as grain boundaries and point defects, their implementation at the device scale to assess the active defect distribution and their impact on field-induced channel charge modulation and current transport is strictly restrained. Therefore, it becomes critical to directly probe the gate modulation effect on the carrier population at the nanoscale of an FET channel, with the objective to establish a direct correlation with the device characteristics. Here, we have investigated the active channel in a monolayer MoS2 FET through in situ scanning probe microscopy, namely, Kelvin probe force microscopy and scanning capacitance microscopy, to directly identify active defect sites and to improve our understanding of the contribution of grain boundaries, bilayer islands, and defective grain domains to channel conductance.

Insulating 6,6-Phenyl-C61-butyric Acid Methyl Ester on Transition-Metal Dichalcogenides: Impact of the Hybrid Materials on the Optical and Electrical Properties

In this study we develop a strategy to insulate 6,6 -Phenyl C61 butyric acid methyl ester (PCBM) on the basal plane of transition metal dichalcogenides (TMDs). Concretely single layers of MoS2, MoSe2, MoTe2, WS2, WSe2 and WTe2 and ultrathin MoO2 and WO2 were grown via chemical vapor deposition (CVD). Then, the thiol group of a PCBM modified with cysteine reacts with the chalcogen vacancies on the basal plane of TMDs, yielding PCBM-MoS2, PCBM-MoSe2, PCBM-WS2, PCBM-WSe2, PCBM-WTe2, PCBM-MoO2 and PCBM-WO2. Afterwards, all the hybrid materials were characterized using several techniques, including XPS, Raman spectroscopy, TEM, AFM, and cyclic voltammetry. Furthermore, PCBM causes a unique optical and electrical impact in every TMDs. For MoS2 devices, the conductivity and photoluminescence (PL) emission achieve a remarkable enhancement of 1700 % and 200 % in PCBM-MoS2 hybrids. Similarly, PCBM-MoTe2 hybrids exhibit a 2-fold enhancement in PL emission at 1.1 eV. On the other hand, PCBM-MoSe2, PCBM-WSe2 and PCBM-WS2 hybrids exhibited a new interlayer exciton at 1.29-1.44, 1.7 and 1.37-154 eV along with an enhancement of the photo-response by 2400, 3200 and 600 %, respectively. Additionally, PCBM-WTe2 and PCBM-WO2 showed a modest photo-response, in sharp contrast with pristine WTe2 or WO2 which archive pure metallic character.

Rewritable printing of ionic liquid nanofilm utilizing focused ion beam induced film wetting

Manipulating liquid flow over open solid substrate at nanoscale is important for printing, sensing, and energy devices. The predominant methods of liquid maneuvering usually involve complicated surface fabrications, while recent attempts employing external stimuli face difficulties in attaining nanoscale flow control. Here we report a largely unexplored ion beam induced film wetting (IBFW) technology for open surface nanofluidics. Local electrostatic forces, which are generated by the unique charging effect of Helium focused ion beam (HFIB), induce precursor film of ionic liquid and the disjoining pressure propels and stabilizes the nanofilm with desired patterns. The IBFW technique eliminates the complicated surface fabrication procedures to achieve nanoscale flow in a controllable and rewritable manner. By combining with electrochemical deposition, various solid materials with desired patterns can be produced.

Nanoscale Channel Length MoS2 Vertical Field-Effect Transistor Arrays with Side-Wall Source/Drain Electrodes

Two-dimensional transition metal dichalcogenides (TMDCs) have natural advantages in overcoming the short-channel effect in field-effect transistors (FETs) and in fabricating three-dimensional FETs, which benefit in increasing device density. However, so far, most reported works related to MoS2 FETs with a sub-100 nm channel employ mechanically exfoliated materials and all of the works involve electron beam lithography (EBL), which may limit their application in fabricating wafer-scale device arrays as demanded in integrated circuits (ICs). In this work, MoS2 FET arrays with a side-wall source and drain electrodes vertically distributed are designed and fabricated. The channel length of the as-fabricated FET is basically determined by the thickness of an insulating layer between the source and drain electrodes. The vertically distributed source and drain electrodes enable to reduce the electrode-occupied area and increase in the device density. The as-fabricated vertical FETs exhibit on/off ratios comparable to those of mechanically exfoliated MoS2 FETs with a nanoscale channel length under identical VDS. In addition, the as-fabricated FETs can work at a VDS as low as 10 mV with a desirable on/off ratio (1.9 × 107), which benefits in developing low-power devices. Moreover, the fabrication process is free from EBL and can be applied to wafer-scale device arrays. The statistical results show that the fabricated FET arrays have a device yield of 87.5% and an average on/off ratio of about 1.7 × 106 at a VDS of 10 mV, with the lowest and highest ones to be about 1.3 × 104 and 1.9 × 107, respectively, demonstrating the good reliability of our fabrication process. Our work promises a bright future for TMDCs in realizing high-density and low-power nanoelectronic devices in ICs.

Aligned carbon nanotube-based electronics on glass wafer

Carbon nanotubes (CNTs), due to excellent electronic properties, are emerging as a promising semiconductor for diverse electronic applications with superiority over silicon. However, until now, the supposed superiority of CNTs by "head-to-head" comparison within a well-defined voltage range remains unrealized. Here, we report aligned CNT (ACNT)-based electronics on a glass wafer and successfully develop a 250-nm gate length ACNT-based field-effect transistor (FET) with an almost identical transfer curve to a "90-nm" node silicon device, indicating a three- to four-generation superiority. Moreover, a record gate delay of 9.86 ps is achieved by our ring oscillator, which exceeds silicon even at a lower supply voltage. Furthermore, the fabrication of basic logic gates indicates the potential for further digital integrated circuits. All of these results highlight ACNT-based FETs on the glass wafer as an effective solution/platform for further development of CNT-based electronics.